FPGA-in-the-Loop Simulation
R2026bVerification with FPGA hardware
Run a Simulink® or MATLAB® simulation that is synchronized with an HDL design running on an Microchip board.
Apps
| FPGA-in-the-Loop Wizard | Generate an FPGA-in-the-loop (FIL) block or System object from existing HDL files |
| Logic Analyzer | Visualize, measure, and analyze transitions and states over time |
Functions
filProgramFPGA | Load programming file onto FPGA |
programFPGA | Load programming file associated with FILSimulation or FILFreeRunning system
object onto FPGA |
Objects
hdlverifier.FILSimulation | FIL simulation with MATLAB |
Blocks
 | FIL Simulation | Simulate HDL code on FPGA hardware from Simulink |
Topics
- FPGA-in-the-Loop Simulation
FPGA-in-the-loop (FIL) simulation provides the capability to use Simulink or MATLAB software for testing designs in real hardware for any existing HDL code.
- FPGA-in-the-Loop Simulation Workflows
Choose between generating a block or System object™, and decide whether to use the FIL Wizard or HDL Workflow Advisor.
Featured Examples
Verify HDL Implementation of PID Controller Using FPGA-in-the-Loop for Altera and Microchip Devices
Set up an FPGA-in-the-Loop (FIL) application using HDL Coder™.
