Dual Port RAM

R2026b

(To be removed) Dual port RAM with two output ports

Dual Port RAM will be removed in a future release. Use the Dual Port RAM System instead.

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Dual Port RAM block

To add a block to a model, double-click the canvas and start typing the block name. Then, select the block from the list.

Libraries:
HDL Coder / HDL RAMs

Description

The Dual Port RAM block models a RAM that supports simultaneous read and write operations, and has both a read data output port and write data output port. You can use this block to generate HDL code that maps to RAM in most FPGAs.

If you do not need to use the write output data, wr_dout, you can achieve better RAM inference with synthesis tools by using the Simple Dual Port RAM block.

Read-During-Write Behavior

During a write, new data appears at the output of the write port (wr_dout) of the Dual Port RAM block. If a read operation occurs simultaneously at the same address as a write operation, old data appears at the read output port (rd_dout).

Ports

Input

wr_din — Write data input

Scalar (default)

Data that you write into the RAM memory location when wr_en is true. The data inherits the width and data type from the input signal. wr_din can be a double, single, integer, or a fixed-point (fi) object, and can be real or complex.

Data type: scalar fixed point, integer, or complex

Data Types: int8 | int16 | int32 | int64 | Boolean | fixed point

wr_addr — Write address

Scalar (default)

Address that you write the data into when wr_en is true. This value can be either fixed-point(fi) or integer, must be unsigned, and have a fraction length of 0.

Data Types: uint8 | uint16 | uint32 | uint64 | fixed point

wr_en — Write enable

Scalar (default)

When wr_en is true, the RAM writes the data into the memory location that you specify.

Data Types: Boolean

rd_addr — Read address

Scalar (default)

Address that you read the data from. This value can be either fixed-point(fi) or integer, must be unsigned, and have a fraction length of 0.

Data Types: uint8 | uint16 | uint32 | uint64 | fixed point

Output

wr_dout — Output data from write address

Scalar (default)

Output data from write address, wr_addr.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point | enumerated | bus

rd_dout — Output data from read address

Scalar (default)

Output data from read address, rd_addr.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point | enumerated | bus

Parameters

Address port width — Address bit width

8 (default)

Minimum bit width is 2, and maximum bit width is 29.

Programmatic Use

Block parameter: ram_size

Type: string scalar | character vector

Value: A minimum value of 2 and maximum value of 29

Default: '8'

Programmatic Use: Add Block

To add the block programmatically, use the add_block function with one of these library block paths as the source.

"hdlsllib/HDL RAMs/Dual Port RAM"

Example: add_block("hdlsllib/HDL RAMs/Dual Port RAM","myModel/myBlock",MakeNameUnique="on")

Algorithms

HDL code generated for RAM blocks has:

• A latency of one clock cycle for read data output.

• No reset signal, because some synthesis tools do not infer a RAM from HDL code if it includes a reset.

Code generation for a RAM block creates a separate file, blockname.ext. blockname is derived from the name of the RAM block. ext is the target language file name extension.

RAM Initialization

Code generated to initialize a RAM is intended for simulation only. Synthesis tools can ignore this code.

Implement RAM With or Without Clock Enable

The HDL block property, RAMArchitecture, enables or suppresses generation of clock enable logic for all RAM blocks in a subsystem. You can set RAMArchitecture to the following values:

• WithClockEnable (default): Generates RAMs using HDL templates that include a clock enable signal, and an empty RAM wrapper.

• WithoutClockEnable: Generates RAMs without clock enables, and a RAM wrapper that implements the clock enable logic.

Some synthesis tools do not infer RAMs with a clock enable. If your synthesis tool does not support RAM structures with a clock enable, and cannot map your generated HDL code to FPGA RAM resources, set RAMArchitecture to 'WithoutClockEnable'. To learn how to generate RAMs without clock enables for your design, see the Getting Started with RAM and ROM example. To open the example, at the command prompt, enter:

openExample('hdlcoder/GettingStartedWithRAMAndROMInSimulinkExample')

RAM Inference Limitations

If you use RAM blocks to perform concurrent read and write operations, verify the read-during-write behavior in hardware. The read-during-write behavior of the RAM blocks in Simulink^® matches that of the generated behavioral HDL code. However, if a synthesis tool does not follow the same behavior during RAM inference, it causes the read-during-write behavior in hardware to differ from the behavior of the Simulink model or generated HDL code.

Your synthesis tool might not map the generated code to RAM for the following reasons:

• Small RAM size: your synthesis tool uses registers to implement a small RAM for better performance.

• A clock enable signal is present. You can suppress generation of a clock enable signal in RAM blocks, as described in Implement RAM With or Without Clock Enable.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

General
ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays in the design. Distributed pipelining does not redistribute these registers. The default value is 0. For more details, see ConstrainedOutputPipeline.
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default value is 0. For more details, see InputPipeline.
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default value is 0. For more details, see OutputPipeline.
SynthesisAttributes	Specifies the synthesis attributes for the blocks and block output signals in the model. The generated HDL code contains these attributes. For more information, see SynthesisAttributes.

Complex Data Support

This block supports code generation for complex signals.

Dual Port RAM System

The Dual Port RAM System block implementation uses a MATLAB System block that uses the hdl.RAM System object™. Use this block to perform simultaneous read and write operations. It has a read data output port and a write data output port. In the Block Parameters dialog box of the block, you can specify an initial value for the RAM. If you do not want to use the write data output port, to achieve better RAM inference, use the Simple Dual Port RAM System block instead.

Use this block to replace the Dual Port RAM block in your model. You obtain faster simulation results when using this block in your model.

Version History

Introduced in R2014a

R2026a: RAMDirective HDL block property has been removed

The RAMDirective HDL block property has been removed. To map RAM blocks in your design to the RAM blocks on the target FPGA, use the SynthesisAttributes HDL block property instead.

R2026a: Specify synthesis attributes for blocks and block output signals

Use the SynthesisAttributes HDL block property to specify the synthesis attributes for the block and its output signals. HDL Coder includes these attributes in the generated HDL code.

R2024b: To be removed

The Dual Port RAM is no longer recommended. This block will be removed in a future release. Instead, use the Dual Port RAM System block. For more information, see Dual Port RAM System.