True Dual Port RAM System

True Dual Port RAM block based on the hdl.RAM system object with ability to provide initial value

Since R2023b

• 

Libraries:
HDL Coder / HDL RAMs

Description

The blocks are MATLAB System blocks that use the hdl.RAM System object™. You can specify the RAM type as Dual port, Simple dual port, Single port, True dual port, or Simple tri port. With the MATLAB System blocks, you can:

• Specify an initial value for the RAM. In the Block Parameters dialog box, enter a value for Specify the RAM initial value.

• Obtain faster simulation results when you use these blocks in your Simulink^® model.

• Create parallel RAM banks when you use vector data by leveraging the hdl.RAM System object functionality.

• Obtain higher performance and support for large data memories.

Limitations

• When you build the FPGA bitstream for the RAM, the global reset logic does not reset the RAM contents. To reset the RAM, implement the reset logic.

• The RAM write address can be either fixed-point (fi) or integer, must be unsigned, and must be between 2 and 31 bits long.

Ports

Input

din_a — Write data input

scalar | vector

Data to write into the RAM memory location when the signal at port we_a is true. This value can be double, single, half, integer, Boolean or a fixed-point (fi) object, and can be real or complex.

Bus Support:

You can use non-virtual bus and array of buses at the data port for HDL code generation.

Data Types: single | double | half | int8 | int16 | uint8 | uint16 | Boolean | fixed point

addr_a — Write address

scalar | vector

RAM address to write the data from port din_a to. This value can be either fixed-point (fi) or integer, must be unsigned, and must be between 2 and 31 bits long. The values at port addr_a and addr_b cannot be the same address.

Data Types: uint8 | uint16 | fixed point

we_a — Write enable

scalar | vector

When the signal at this port is true, the block writes the data from port din_a to the memory location specified by port addr_a.

Data Types: Boolean

din_b — Write data input

scalar | vector

Data to write to the RAM memory location when the signal at port we_b is true. This value can be double, single, integer, or a fixed-point (fi) object, and can be real or complex.

Data Types: single | double | int8 | int16 | uint8 | uint16 | fixed point

addr_b — Write address

scalar | vector

RAM address to write the data from port din_b to. This value can be either fixed-point (fi) or integer, must be unsigned, and must be between 2 and 31 bits long. The values at port addr_a and addr_b cannot be the same address.

Data Types: uint8 | uint16 | fixed point

we_b — Write enable

scalar | vector

When the signal at this port is true, the RAM writes the data from port din_b to the memory location specified by port addr_b.

Data Types: Boolean

Output

dout_a — Write data output

scalar | vector

New or old output data that the RAM reads from the memory location specified by port addr_a.

dout_b — Write data output

scalar | vector

New or old output data that the RAM reads from the memory location specified by port addr_b.

Parameters

Specify the type of RAM — RAM type

True dual port (default) | Simple dual port | Single port | Dual port | Simple tri port

Type of RAM, specified as either:

• Single port — Create a single port RAM with write data, write address, and write enable as inputs and read data as the output.

• Simple dual port — Create a simple dual-port RAM with write data, write address, write enable, and read address as inputs and data from read address as the output.

• Dual port — Create a dual-port RAM with write data, write address, write enable, and read address as inputs and data from read address and write address as the outputs.

• True dual port — Create a true dual-port RAM with write data a and b, write/read address a and b, and write enable a and b as inputs and data from write address a and b as the outputs.

• Simple tri port — Create a simple tri-port RAM with write data, write address, write enable, and read address a and b as inputs and data from read address a and b as the outputs.

The code generator dynamically configures the input and output ports of the block based on the RAM type that you specify.

Specify the output data for a write operation — Write output behavior

New data (default) | Old data

Behavior for the write output, specified as either:

• New data — Send out new data at the address to the output.

• Old data — Send out old data at the address to the output.

Specify the RAM initial value — Initial simulation output of RAM

0 (default) | scalar | vector

Initial simulation output of the System object block, specified as either:

• A scalar value

• A vector with one-to-one mapping between the initial value and the RAM words

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Architecture

The block has a MATLAB System architecture, which indicates that the block implementation uses the hdl.RAM System object.

HDL Block Properties

General
ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. For more details, see ConstrainedOutputPipeline.
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see InputPipeline.
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see OutputPipeline.
RAMDirective	Specify whether to map RAM blocks in your design to the RAM blocks on the target FPGA. For UltraRAM mapping, Specify the RAM initial value must be set to 0. For more details, see RAMDirective.

Complex Data Support

This block supports code generation for complex signals.

Version History

Introduced in R2023b

R2024a: Array of Buses Input Support

The block now supports HDL code generation for input data specified as an array of buses.

R2024a: Half-Precision and Boolean Data Support

The block now supports HDL code generation with input data of type Half or Boolean.