makehdl

Generate HDL RTL code from model, subsystem, or model reference

Syntax

makehdl(dut)

makehdl(dut,Name,Value)

Description

makehdl(dut) generates HDL code from the specified DUT model, subsystem, or model reference.

Note

Running this command can activate the Open at simulation start setting for blocks such as the Scope block and therefore invoke the block.

makehdl(dut,Name,Value) generates HDL code from the specified DUT model, subsystem, or model reference with options specified by one or more name-value pair arguments.

Examples

Generate VHDL for the Current Model

This example shows how to generate VHDL for the symmetric FIR model.

Open the sfir_fixed model.

sfir_fixed

Generate HDL code for the current model with code generation options set to default values.

makehdl('sfir_fixed/symmetric_fir','TargetDirectory','C:\GenVHDL\hdlsrc')

### Generating HDL for 'sfir_fixed/symmetric_fir'.
### Starting HDL check.
### Begin VHDL Code Generation for 'sfir_fixed'.
### Working on sfir_fixed/symmetric_fir as C:\GenVHDL\hdlsrc\sfir_fixed\symmetric_fir.vhd.
### Creating HDL Code Generation Check Report file://C:\GenVHDL\hdlsrc\sfir_fixed\symmetric_fir_report.html
### HDL check for 'sfir_fixed' complete with 0 errors, 0 warnings, and 0 messages.
### HDL code generation complete.

The generated VHDL code is saved in the hdlsrc folder.

Generate Verilog for a Subsystem Within a Model

Generate Verilog® for the subsystem symmetric_fir within the model sfir_fixed.

Open the sfir_fixed model.

sfir_fixed;

The model opens in a new Simulink® window.

Generate Verilog for the symmetric_fir subsystem.

makehdl('sfir_fixed/symmetric_fir', 'TargetLanguage', 'Verilog', ...
               'TargetDirectory', 'C:/Generate_Verilog/hdlsrc')

### Generating HDL for 'sfir_fixed/symmetric_fir'.
### Starting HDL check.
### Begin Verilog Code Generation for 'sfir_fixed'.
### Working on sfir_fixed/symmetric_fir as C:\Generate_Verilog\hdlsrc\sfir_fixed\symmetric_fir.v.
### Creating HDL Code Generation Check Report file://C:\Generate_Verilog\hdlsrc\sfir_fixed\symmetric_fir_report.html
### HDL check for 'sfir_fixed' complete with 0 errors, 0 warnings, and 0 messages.
### HDL code generation complete.

The generated Verilog code for the symmetric_fir subsystem is saved in hdlsrc\sfir_fixed\symmetric_fir.v.

Close the model.

bdclose('sfir_fixed');

Generate SystemVerilog code for a Subsystem Within a Model

Generate SystemVerilog code for the subsystem symmetric_fir within the model sfir_fixed.

Open the sfir_fixed model.

sfir_fixed;

The model opens in a new Simulink® window.

Generate SystemVerilog code for the symmetric_fir subsystem.

makehdl('sfir_fixed/symmetric_fir', 'TargetLanguage', 'SystemVerilog', ...
               'TargetDirectory', 'C:/Generate_SV/hdlsrc')

### Generating HDL for 'sfir_fixed/symmetric_fir'.
### Using the config set for model <a href="matlab:configset.showParameterGroup('sfir_fixed', { 'HDL Code Generation' } )">sfir_fixed</a> for HDL code generation parameters.
### Running HDL checks on the model 'sfir_fixed'.
### Begin compilation of the model 'sfir_fixed'...
### Working on the model 'sfir_fixed'...
### Working on... <a href="matlab:configset.internal.open('sfir_fixed', 'GenerateModel')">GenerateModel</a>
### Begin model generation 'gm_sfir_fixed' ....
### Copying DUT to the generated model....
### Model generation complete.
### Begin SystemVerilog Code Generation for 'sfir_fixed'.
### Working on sfir_fixed/symmetric_fir as C:\Generate_SV\hdlsrc\sfir_fixed\symmetric_fir.sv.
### Code Generation for 'sfir_fixed' completed.
### Creating HDL Code Generation Check Report file:///C:/Generate_SV/hdlsrc/sfir_fixed/symmetric_fir_report.html
### HDL check for 'sfir_fixed' complete with 0 errors, 0 warnings, and 0 messages.
### HDL code generation complete.

The generated SystemVerilog code for the symmetric_fir subsystem is saved in hdlsrc\sfir_fixed\symmetric_fir.sv.

Close the model.

bdclose('sfir_fixed');

Check Subsystem for Compatibility with HDL Code Generation

Check that the subsystem symmetric_fir is compatible with HDL code generation, then generate HDL.

Open the sfir_fixed model.

sfir_fixed

The model opens in a new Simulink® window.

Use the checkhdl function to check whether the symmetric_fir subsystem is compatible with HDL code generation.

hdlset_param('sfir_fixed','TargetDirectory','C:/HDL_Checks/hdlsrc');
checkhdl('sfir_fixed/symmetric_fir')

### Starting HDL check.
### Creating HDL Code Generation Check Report file://C:\HDL_Checks\hdlsrc\sfir_fixed\symmetric_fir_report.html
### HDL check for 'sfir_fixed' complete with 0 errors, 0 warnings, and 0 messages.

checkhdl completed successfully, which means that the model is compatible for HDL code generation. To generate code, use makehdl

makehdl('sfir_fixed/symmetric_fir')

### Generating HDL for 'sfir_fixed/symmetric_fir'.
### Using the config set for model <a href="matlab:configset.showParameterGroup('sfir_fixed', { 'HDL Code Generation' } )">sfir_fixed</a> for HDL code generation parameters.
### Starting HDL check.
### Begin VHDL Code Generation for 'sfir_fixed'.
### Working on sfir_fixed/symmetric_fir as C:\HDL_Checks\hdlsrc\sfir_fixed\symmetric_fir.vhd.
### Creating HDL Code Generation Check Report file://C:\HDL_Checks\hdlsrc\sfir_fixed\symmetric_fir_report.html
### HDL check for 'sfir_fixed' complete with 0 errors, 0 warnings, and 0 messages.
### HDL code generation complete.

The generated VHDL® code for the symmetric_fir subsystem is saved in hdlsrc\sfir_fixed\symmetric_fir.vhd.

Close the model.

bdclose('sfir_fixed');

Input Arguments

dut — DUT model or subsystem name

character vector

Specified as subsystem name, top-level model name, or model reference name with full hierarchical path.

Example: 'top_level_name'

Example: 'top_level_name/subsysA/subsysB/codegen_subsys_name'

Name-Value Arguments

Specify optional pairs of arguments as Name1=Value1,...,NameN=ValueN, where Name is the argument name and Value is the corresponding value. Name-value arguments must appear after other arguments, but the order of the pairs does not matter.

Before R2021a, use commas to separate each name and value, and enclose Name in quotes.

Example: 'TargetLanguage','Verilog'

Target Language and Folder Selection Options

HDLSubsystem — DUT Subsystem

character vector

Specify the Subsystem in your model to generate HDL code for. For more information, see Generate HDL for.

TargetLanguage — Target language

'VHDL' (default) | 'Verilog' | 'SystemVerilog'

Specify whether to generate VHDL or Verilog code. For more information, see Language.

TargetDirectory — Output directory

'hdlsrc' (default) | character vector

Specify a path to write the generated files and HDL code into. For more information, see Code Generation Folder.

Tool and Synthesis Options

SynthesisTool — Synthesis tool

'' (default) | 'Altera Quartus II' | 'Xilinx ISE' | 'Xilinx Vivado' | 'Intel Quartus Pro' | 'Microchip Libero SoC'

Specify the synthesis tool for targeting the generated HDL code as a character vector. For more information, see Synthesis Tool.

SynthesisToolChipFamily — Synthesis tool chip family

'' (default) | character vector

Specify the synthesis tool chip family for the target device as a character vector. For more information, see Family.

SynthesisToolDeviceName — Synthesis tool device name

'' (default) | character vector

Specify the synthesis tool device name for the target device as a character vector. For more information, see Device.

SynthesisToolPackageName — Synthesis tool package name

'' (default) | character vector

Specify the synthesis tool package name for the target device as a character vector. For more information, see Package.

SynthesisToolSpeedValue — Synthesis tool speed value

'' (default) | character vector

Specify the synthesis tool speed value for the target device as a character vector. For more information, see Speed.

TargetFrequency — Target frequency in MHz

'' (default) | character vector

Specify the target frequency in MHz as a character vector. For more information, see Target Frequency.

General Optimizations and Multicycle Path Constraints Settings

BalanceDelays — Delay balancing

'on' (default) | 'off'

Specify whether to enable delay balancing on the model. For more information, see Balance delays.

RAMMappingThreshold — Minimum RAM size for mapping to RAMs instead of registers

256 (default) | positive integer | string of format "MxN"

Specify the minimum RAM size required for mapping to RAMs instead of registers. You can specify either:

• A single integer to define the mapping threshold that maps any delay or persistent array greater than that threshold bit size to RAM.

• A string that define two thresholds, one for delay length or array size and one for word length.

For more information, see RAM mapping threshold.

MapPipelineDelaysToRAM — Map pipeline registers in the generated HDL code to RAM

'off' (default) | 'on'

Specify whether to map pipeline registers in the generated HDL code to block RAMs on the FPGA. For more information, see Map pipeline delays to RAM.

TransformNonZeroInitValDelay — Transform delays with nonzero initial value

'on' (default) | 'off'

Specify whether to transform Delay blocks that have nonzero initial value to Delay blocks that have a zero initial value. For more information, see Transform non zero initial value delay.

MultiplierPartitioningThreshold — Partition multipliers based on a threshold

'Inf' (default) | positive integer

Partition multipliers in the design based on a threshold value. The threshold must be a positive integer value, N. For more information, see Multiplier partitioning threshold.

DeleteUnusedPorts — Removes ports in your design that are unused from the generated HDL code

'on' (default) | 'off'

For more information, see Remove Unused Ports.

MulticyclePathConstraints — Enable-based multicycle path constraint file generation

'off' (default) | 'on'

Generate an enable-based multicycle path constraints file. For more information, see Enable-based constraints.

Pipelining and Speed Optimization Options

PipelineDistributionPriority — Specify priority for distributed pipelining and delay absorption algorithms

'Numerical Integrity' (default) | 'Performance'

Whether to prioritize numerical integrity or performance for distributed pipelining and delay absorption, specified as 'Numerical Integrity' or 'Performance'. For more information, see Pipeline distribution priority.

AllowDelayDistribution — Allow design delay distribution

'off' (default) | 'on'

Option to allow design delay distribution during distributed pipelining and delay absorption, specified as 'off' or 'on'. For more information, see Allow design delay distribution.

UseSynthesisEstimatesForDistributedPipelining — Use synthesis estimates for distributed pipelining

'off' (default) | 'on'

Use synthesis timing estimates for distributed pipelining to more accurately reflect how components function on hardware to better distribute pipelines and increase clock speed for your target device. For more information, see Use synthesis estimates for distributed pipelining.

ClockRatePipelining — Insert pipeline registers at the clock rate instead of the data rate for multi-cycle paths

'on' (default) | 'off'

Insert pipeline registers at the clock rate instead of the data rate for multi-cycle paths. For more information, see Clock-rate pipelining.

ClockRatePipelineOutputPorts — Clock-rate pipelining for DUT ports

'on' (default) | 'off'

Enable clock-rate pipelining for DUT ports. For more information, see Allow clock-rate pipelining of DUT output ports.

AdaptivePipelining — Insert adaptive pipelines

'off' (default) | 'on'

Insert adaptive pipeline registers in your design. For more information, see Adaptive pipelining.

Resource Sharing and Area Optimization Options

ShareAdders — Share adders in the design

'off' (default) | 'on'

Use resource sharing optimization to share adders in your design. For more information, see Share Adders.

AdderSharingMinimumBitwidth — Minimum bitwidth of shared adder for resource sharing

0 (default) | positive integer

Minimum bitwidth of a shared adder for the resource sharing optimization, specified as a positive integer. For more information, see Adder sharing minimum bitwidth.

ShareMultipliers — Share multipliers in the design

'on' (default) | 'on'

Use resource sharing optimization to share multipliers in your design. For more information, see Share Multipliers.

MultiplierSharingMinimumBitwidth — Minimum bitwidth of shared multiplier for resource sharing

0 (default) | positive integer

Minimum bitwidth of a shared multiplier for the resource sharing optimization, specified as a positive integer. For more information, see Multiplier sharing minimum bitwidth.

MultiplierPromotionThreshold — Minimum promotion wordlength

0 (default) | positive integer

Minimum wordlength by which the code generator promotes a multiplier for sharing with other multipliers. For more information, see Multiplier promotion threshold.

ShareMultiplyAdds — Share Multiply-Add blocks in the design

'on' (default) | 'on'

Use resource sharing optimization to share Multiply-Add blocks in your design. For more information, see Share Multipliers.

MultiplyAddSharingMinimumBitwidth — Minimum bitwidth of shared Multiply-Add block for resource sharing

0 (default) | positive integer

Minimum bitwidth of a shared Multiply-Add block for the resource sharing optimization, specified as a positive integer. For more information, see Multiply-Add block sharing minimum bitwidth.

ShareAtomicSubsystems — Share atomic subsystems in the design

'on' (default) | 'on'

Use resource sharing optimization to share Atomic Subsystem blocks in your design. For more information, see Atomic subsystems.

ShareMATLABBlocks — Share MATLAB Function blocks in the design

'on' (default) | 'on'

Use resource sharing optimization to share MATLAB Function blocks in your design. For more information, see MATLAB Function blocks.

ShareFloatingPointIPs — Share floating-point IPs in the design

'on' (default) | 'on'

Use resource sharing optimization to share floating-point IPs in your design. For more information, see Floating-Point IPs.

Floating Point Target

FloatingPointTargetConfiguration — Floating point target configuration

'' (default) | character vector

For more information, see Vendor Specific Floating Point Library.

Code Generation Report Options

Traceability — Generate report with mapping links between HDL and model

'off' (default) | 'on'

Generate a traceability report that has hyperlinks for navigating from code-to-model and from model-to-code. For more information, see Generate traceability report.

TraceabilityStyle — Line-level or comment-based traceability style

'Line Level' (default) | 'Comment Based'

Generate a traceability report that has hyperlinks from each line or to a comment indicating block of code for navigating from code-to-model and from model-to-code. For more information, see Traceability style.

ResourceReport — Resource utilization report generation

'off' (default) | 'on'

Generate a resource utilization report that displays the number of hardware resources that the generated HDL code uses. For more information, see Generate resource utilization report.

OptimizationReport — Optimization report generation

'off' (default) | 'on'

Generate an optimization report that displays the effect of optimizations such as streaming, sharing, and distributed pipelining. For more information, see Generate optimization report.

HDLGenerateWebview — Include model Web view

'on' (default) | 'off'

Generate a web view of the model in the Code Generation report to easily navigate between the code and model. For more information, see Generate model Web view.

Clock Settings

ResetType — Reset type

'async' (default) | 'sync'

Specify whether to use synchronous or asynchronous reset in the generated HDL code. For more information, see Reset type.

ResetAssertedLevel — Asserted (active) level of reset

'active-high' (default) | 'active-low'

Specify whether to use an active-high or active-low asserted level for the reset input signal. For more information, see Reset asserted level.

ClockInputPort — Clock input port name

'clk' (default) | character vector

Specify the clock input port name as a character vector. For more information, see Clock input port.

ClockEnableInputPort — Clock enable input port name

'clk_enable' (default) | character vector

Specify the clock enable input port name as a character vector. For more information, see Clock enable input port.

ResetInputPort — Reset input port name

'reset' (default) | character vector

Reset input port name, specified as a character vector.

For more information, see Reset input port.

ClockEdge — Active clock edge

'Rising' (default) | 'Falling'

Specify the active clock edge for the generated HDL code. For more information, see Clock edge

ClockInputs — Single or multiple clock inputs

'Single' (default) | 'Multiple'

Specify whether to generate single or multiple clock inputs in the HDL code. For more information, see Clock inputs.

Oversampling — Oversampling factor for global clock

1 (default) | integer greater than or equal to 0

Frequency of global oversampling clock, specified as an integer multiple of the model’s base rate. For more information, see Treat Simulink rates as actual hardware rates and Oversampling factor.

General File and Variable Name Options

UserComment — HDL file header comment

character vector

Specify comment lines in header of generated HDL and test bench files. For more information, see Comment in header.

VerilogFileExtension — Verilog^® file extension

'.v' (default) | character vector

Specify the file name extension for generated Verilog files. For more information, see Verilog file extension.

VHDLFileExtension — VHDL^® file extension

'.vhd' (default) | character vector

Specify the file name extension for generated VHDL files. For more information, see VHDL file extension.

EntityConflictPostfix — Postfix for duplicate VHDL entity or Verilog module names

'_block' (default) | character vector

Specify the postfix as a character vector that resolves duplicate entity or module names. For more information, see Entity conflict postfix.

PackagePostfix — Postfix for package file name

'_pkg' (default) | character vector

Specify the postfix for the package file name as a character vector. For more information, see Package postfix.

ReservedWordPostfix — Postfix for names conflicting with VHDL or Verilog reserved words

'_rsvd' (default) | character vector

For more information, see Reserved word postfix.

SplitEntityArch — Split VHDL entity and architecture into separate files

'off' (default) | 'on'

For more information, see Split entity and architecture.

SplitEntityFilePostfix — Postfix for VHDL entity file names

'_entity' (default) | character vector

For more information, see Split entity file postfix.

SplitArchFilePostfix — Postfix for VHDL architecture file names

'_arch' (default) | character vector

For more information, see Split arch file postfix.

VHDLArchitectureName — VHDL architecture name

'rtl' (default) | character vector

For more information, see VHDL architecture name.

ClockProcessPostfix — Postfix for clock process names

'_process' (default) | character vector

Specify the postfix for clocked process names as a character vector. For more information, see Clocked process postfix.

ComplexImagPostfix — Postfix for imaginary part of complex signal

'_im' (default) | character vector

For more information, see Complex imaginary part postfix.

ComplexRealPostfix — Postfix for imaginary part of complex signal names

'_re' (default) | character vector

For more information, see Complex real part postfix.

EnablePrefix — Prefix for internal enable signals

'enb' (default) | character vector

Prefix for internal clock enable and control flow enable signals, specified as a character vector. For more information, see Clock enable input port and Enable prefix.

ModulePrefix — Prefix for modules or entity names

'' (default) | character vector

Specify a prefix for every module or entity name in the generated HDL code. HDL Coder™ also applies this prefix to generated script file names

For more information, see Module name prefix.

TimingControllerPostfix — Postfix for timing controller name

'_tc' (default) | character vector

For more information, see Timing controller postfix.

PipelinePostfix — Postfix for input and output pipeline register names

'_pipe' (default) | character vector

For more information, see Pipeline postfix.

VHDLLibraryName — VHDL library name

'work' (default) | character vector

For more information, see VHDL library name.

UseSingleLibrary — Generate VHDL code for model references into a single library

'off' (default) | 'on'

For more information, see Generate VHDL or SystemVerilog code for model references into a single library.

BlockGenerateLabel — Block label postfix for VHDL GENERATE statements

'_gen' (default) | character vector

For more information, see Block generate label.

OutputGenerateLabel — Output assignment label postfix for VHDL GENERATE statements

'outputgen' (default) | character vector

For more information, see Output generate label.

InstanceGenerateLabel — Instance section label postfix for VHDL GENERATE statements

'_gen' (default) | character vector

For more information, see Instance generate label.

InstancePostfix — Postfix for generated component instance names

'' (default) | character vector

For more information, see Instance postfix.

InstancePrefix — Prefix for generated component instance names

'u_' (default) | character vector

For more information, see Instance prefix.

VectorPrefix — Prefix for vector names

'vector_of_' (default) | character vector

For more information, see Vector prefix.

HDLMapFilePostfix — Postfix for mapping file

'_map.txt' (default) | character vector

For more information, see Map file postfix.

Configuration Options for Ports

InputType — HDL data type for input ports

'wire' or 'std_logic_vector' (default) | 'signed/unsigned'

VHDL inputs can have 'std_logic_vector' or 'signed/unsigned' data type. Verilog inputs must be 'wire'.

For more information, see Input data type.

OutputType — HDL data type for output ports

'Same as input data type' (default) | 'std_logic_vector' | 'signed/unsigned' | 'wire'

VHDL output can be 'Same as input data type', 'std_logic_vector' or 'signed/unsigned'. Verilog output must be 'wire'.

For more information, see Output data type.

ClockEnableOutputPort — Clock enable output port name

'ce_out' (default) | character vector

Clock enable output port name, specified as a character vector.

For more information, see Clock enable output port.

MinimizeClockEnables — Omit clock enable logic for single-rate designs

'off' (default) | 'on'

For more information, see Minimize clock enables.

MinimizeGlobalResets — Omit global reset logic for single-rate designs

'off' (default) | 'on'

For more information, see Minimize global resets.

TriggerAsClock — Use trigger signal as clock in triggered subsystems

'off' (default) | 'on'

For more information, see Use trigger signal as clock.

EnableTestPoints — Enable HDL DUT port generation for test points

'off' (default) | 'on'

For more information, see Enable HDL DUT output port generation for test points.

ScalarizePorts — Flatten vector ports into scalar ports

'off' (default) | 'on' | 'dutlevel'

For more information, see Scalarize ports.

Coding Style

UseAggregatesForConst — Represent constant values with aggregates

'off' (default) | 'on'

For more information, see Represent constant values by aggregates.

InlineMATLABBlockCode — Inline HDL code for MATLAB Function blocks

'off' (default) | 'on'

For more information, see Inline MATLAB Function block code.

InitializeBlockRAM — Initial signal value generation for RAM blocks

'on' (default) | 'off'

For more information, see Initialize all RAM blocks.

RAMArchitecture — RAM architecture

'WithClockEnable' (default) | 'WithoutClockEnable'

For more information, see RAM Architecture.

NoResetInitializationMode — Initialize no-reset registers

'InsideModule' (default) | 'None' | 'Script'

For more information, see No-reset registers initialization.

MinimizeIntermediateSignals — Minimize intermediate signals

'off' (default) | 'on'

For more information, see Minimize intermediate signals.

LoopUnrolling — Unroll FOR and GENERATE loops

'off' (default) | 'on'

For more information, see Unroll For-Generate Loops.

MaskParameterAsGeneric — Reusable code generation for subsystems with identical mask parameters

'off' (default) | 'on'

For more information, see Generate parameterized HDL code from masked subsystem.

EnumEncodingScheme — Unroll VHDL FOR and GENERATE loops

'default' (default) | 'onehot' | 'twohot' | 'binary'

For more information, see Enumerated Type Encoding Scheme.

ScalarizedPortIndexing — Starting index for the names of scalarized vector ports

'Zero-based' (default) | 'One-based'

For more information, see Indexing for scalarized port naming.

UseRisingEdge — Use VHDL rising_edge or falling_edge function to detect clock transitions

'off' (default) | 'on'

For more information, see Use “rising_edge/falling_edge” style for registers.

InlineConfigurations — Include VHDL configurations

'on' (default) | 'off'

For more information, see Inline VHDL configuration.

SafeZeroConcat — Type-safe syntax for concatenated zeros

'on' (default) | 'off'

For more information, see Concatenate type safe zeros.

ObfuscateGeneratedHDLCode — Obfuscate generated HDL code

'off' (default) | 'on'

Specify whether you want to obfuscate the generated HDL code. For more information, see Generate obfuscated HDL code.

GenerateRecordType — Generate record types for bus

'off' (default) | 'on'

Specify whether you want to generate code with VHDL construct record types for bus signals at design under test (DUT) interface and different subsystem-level interfaces. For more information, see Preserve Bus structure in the generated HDL code.

OptimizeTimingController — Optimize timing controller

'on' (default) | 'off'

For more information, see Optimize timing controller.

TimingControllerArch — Specify the architecture of the generated timing controller

'default' (default) | 'resettable' | 'external'

For more information, see Timing controller architecture.

CustomFileHeaderComment — Custom file header comment

'' (default) | character vector

For more information, see Custom File Header Comment.

CustomFileFooterComment — Custom file footer comment

'' (default) | character vector

For more information, see Custom File Footer Comment.

DateComment — Include time stamp in header

'on' (default) | 'off'

For more information, see Emit time/date stamp in header.

RequirementComments — Link from code generation reports to requirement documents

'on' (default) | 'off'

For more information, see Include requirements in block comments.

UseVerilogTimescale — Generate 'timescale compiler directives

'on' (default) | 'off'

For more information, see Use Verilog or SystemVerilog `timescale directives.

Timescale — Use verilog 'timescale specification

'timescale 1ns/1ns' (default) | character vector

For more information, see Verilog or SystemVerilog timescale specification.

Coding Standards

HDLCodingStandard — Specify HDL coding standard

character vector

Specify whether the generated HDL code must conform to the Industry coding standard guidelines. For more information, see HDL coding standard.

HDLCodingStandardCustomizations — Specify HDL coding standard customization object

hdlcoder.CodingStandard object

Coding standards customization object to use with the Industry coding standard when generating HDL code. For more information, see hdlcoder.CodingStandard.

Model Generation Parameters

GeneratedModel — Output generated model with HDL code

'on' (default) | 'off'

For more information, see Generated model.

GenerateValidationModel — Output validation model with generated model

'off' (default) | 'on'

For more information, see Validation model.

GeneratedModelNamePrefix — Prefix for generated model name

'gm_' (default) | character vector

For more information, see Prefix for generated model name.

ValidationModelNameSuffix — Suffix for generated validation model name

'_vnl' (default) | character vector

For more information, see Suffix for validation model name.

LayoutStyle — Select the layout style of the generated HDL model for better layout visualization

'AutoArrange' (default) | 'Dotty' | 'None'

For more information, see Layout style.

AutoRoute — Automatic signal routing in generated model

'on' (default) | 'off'

For more information, see Auto signal routing.

InterBlkHorzScale — Inter-block horizontal scaling

1.7 (default) | positive integer

For more information, see Inter-block horizontal scaling.

InterBlkVertScale — Inter-block vertical scaling

1.2 (default) | positive integer

For more information, see Inter-block vertical scaling.

Diagnostics and Code Generation Output Parameters

HighlightFeedbackLoops — Highlight feedback loops inhibiting delay balancing and optimizations

'on' (default) | 'off'

Specify whether to highlight feedback loops in your design.

HighlightClockRatePipeliningDiagnostic — Highlight blocks inhibiting clock-rate pipelining

'on' (default) | 'off'

Specify whether to highlight barriers for clock-rate pipelining optimization.

DistributedPipeliningBarriers — Highlight blocks inhibiting distributed pipelining

'on' (default) | 'off'

Specify whether to highlight blocks that inhibit distributed pipelining.

DetectBlackBoxNameCollision — Check for name conflicts in black box interfaces

'warning' (default) | 'none' | 'error'

For more information, see Check for name conflicts in black box interfaces.

TreatRealsInGeneratedCodeAs — Automatic block placement in generated model

'error' (default) | 'warning' | 'none'

For more information, see Check for presence of reals in generated HDL code.

CodeGenerationOutput — Generation of HDL code and display of generated model

'GenerateHDLCode' (default) | 'GenerateHDLCodeAndDisplayGeneratedModel' | 'DisplayGeneratedModelOnly'

Specify whether you want to generate HDL code, or only display the generated model, or generate HDL code and display the generated model. For more information, see Generate HDL code.

GenerateHDLCode — Generate HDL code

'on' (default) | 'off'

Generate HDL code for the model. For more information, see Generate HDL code.

Script Generation

EDAScriptGeneration — Enable or disable script generation for third-party tools

'on' (default) | 'off'

For more information, see Generate EDA scripts.

HDLCompileInit — Compilation script initialization text

'vlib %s\n' (default) | character vector

For more information, see Compile initialization.

HDLCompileTerm — Compilation script termination text

'' (default) | character vector

For more information, see Compile termination.

HDLCompileFilePostfix — Postfix for compilation script file name

'_compile.do' (default) | character vector

For more information, see Compile file postfix.

HDLCompileVerilogCmd — Verilog compilation command

'vlog %s %s\n' (default) | character vector

Verilog compilation command, specified as a character vector. The SimulatorFlags name-value pair specifies the first argument, and the module name specifies the second argument.

For more information, see Compile command for Verilog or SystemVerilog.

HDLCompileVHDLCmd — VHDL compilation command

'vcom %s %s\n' (default) | character vector

VHDL compilation command, specified as a character vector. The SimulatorFlags name-value pair specifies the first argument, and the entity name specifies the second argument.

For more information, see Compile command for VHDL.

HDLLintTool — HDL lint tool

'None' (default) | 'AscentLint' | 'Leda' | 'SpyGlass' | 'Custom'

For more information, see Choose HDL lint tool.

HDLLintInit — HDL lint initialization name

character vector

HDL lint initialization name, specified as a character vector. The default is derived from the HDLLintTool name-value pair.

For more information, see Lint initialization.

HDLLintCmd — HDL lint command

character vector

HDL lint command, specified as a character vector. The default is derived from the HDLLintTool name-value pair.

For more information, see Lint command.

HDLLintTerm — HDL lint termination name

character vector

HDL lint termination, specified as a character vector. The default is derived from the HDLLintTool name-value pair.

For more information, see Lint termination.

HDLSynthTool — Synthesis tool

'None' (default) | 'ISE' | 'Libero' | 'Precision' | 'Quartus' | 'Synplify' | 'Vivado' | 'Custom'

For more information, see Choose synthesis tool.

HDLSynthCmd — HDL synthesis command

character vector

HDL synthesis command, specified as a character vector. The default is derived from the HDLSynthTool name-value pair.

For more information, see Synthesis command.

HDLSynthFilePostfix — Postfix for synthesis script file name

character vector

HDL synthesis script file name postfix, specified as a character vector. The default is derived from the HDLSynthTool name-value pair.

For more information, see Synthesis file postfix.

HDLSynthInit — Synthesis script initialization name

character vector

Initialization for the HDL synthesis script, specified as a character vector. The default is derived from the HDLSynthTool name-value pair.

For more information, see Synthesis initialization.

HDLSynthTerm — Synthesis script termination name

character vector

Termination name for the HDL synthesis script. The default is derived from the HDLSynthTool name-value pair.

For more information, see Synthesis termination.

Version History

Introduced in R2006b