Unit Delay Enabled Synchronous

Delay input signal by one sample period when external Enable signal is true

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Libraries:
HDL Coder / Discrete

Description

The Unit Delay Enabled Synchronous block delays the input signal u by one sample period when the external Enable signal is true. When the Enable signal is false, the state and output signal hold the previous value. The Enable signal is true when E is not zero and false when E is zero.

The Unit Delay Enabled Synchronous block implementation consists of a Synchronous Subsystem that contains an Enabled Delay block with a Delay length of one and a State Control block in Synchronous mode. When you use this block in your model and have HDL Coder™ installed, your model generates cleaner HDL code and uses fewer hardware resources due to the Synchronous behavior of the State Control block.

Limitations

• The block does not support vector inputs on the Enable port.

• You cannot use the block inside Enabled Subsystem, Triggered Subsystem, or Resettable Subsystem blocks that use Classic semantics. The Subsystem must use Synchronous semantics.

Ports

Input

u — Input signal

Scalar | Vector | Matrix | Array | Bus

The Unit Delay Enabled Synchronous block accepts the input signal of the data types listed below. For more information, see Data Types Supported by Simulink.

Data Types: single | double | int8 | int16 | int32 | uint8 | uint16 | uint32 | Boolean | fixed point | enumerated | bus

Input

E — Enable signal

Scalar

The Unit Delay Enabled Synchronous block accepts the Enable signal of the data types listed below. For more information, see Data Types Supported by Simulink.

Data Types: single | double | int8 | int16 | int32 | uint8 | uint16 | uint32 | Boolean | fixed point

Output

y — Output signal

Scalar | Vector | Matrix | Array | Bus

Output data type matches input.

Data Types: single | double | int8 | int16 | int32 | uint8 | uint16 | uint32 | Boolean | fixed point | enumerated | bus

Parameters

Initial condition — Initial output of simulation

0.0 (default) | Scalar | Vector | Matrix | Array | Bus

The Initial condition can take a scalar input or use the same data type as the input signal. You cannot run the simulation with NaN or Inf as the Initial condition.

Programmatic Use

Block parameter: InitialCondition

Type: character vector

Value: '0' | '[n]' | '[m n]'

Default: '0'

Sample time — Time interval between samples

-1 (default) | Scalar | Vector

The Sample time must be a real double scalar that specifies the period or a real double vector of length two that specifies the period and offset. The period and offset must be finite and non-negative with offset less than the period.

Programmatic Use

Block parameter: SampleTime

Type: character vector

Value: '-1' | '[n]' | '[m n]'

Default: '-1'

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

General
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see InputPipeline.
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see OutputPipeline.
ResetType	Suppress reset logic generation. The default is default, which generates reset logic. See also ResetType.

Complex Data Support

This block supports code generation for complex signals.

Restrictions

HDL code generation supports only boolean datatype at the Enable port.

Version History

Introduced in R2017b