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Hierarchical Designs and Synchronous Hardware Behavior

Create subsystems and hierarchical HDL designs with State Control block

The HDL Coder block library contains many blocks that you can add to your Simulink® modeling environment and develop your HDL algorithm. To model large designs, you can divide your model into subsystems and create hierarchical designs. For synchronous hardware behavior and to generate hardware-friendly HDL code, use the State Control block inside the subsystems.

To filter the Simulink Library Browser to show only HDL-supported blocks, enter hdllib. The blocks listed in this section include those blocks that are only available in the HDL Coder library. Blocks such as Foreach Subsystem and Atomic Subsystem are available in the Simulink library in the Library Browser.

For a filtered list of Simulink blocks supported for HDL code generation, see Simulink Block List (HDL Code Generation).

Functions

hdllibDisplay blocks that are compatible with HDL code generation

Simulink Configuration Parameters

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Blocks

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Unit Delay Enabled SynchronousDelay input signal by one sample period when external Enable signal is true
Unit Delay Resettable SynchronousDelay input signal by one sample period when external Reset signal is false
Unit Delay Enabled Resettable SynchronousDelay input signal by one sample period when external Enable signal is true and external Reset signal is false
State ControlSpecify synchronous reset and enable behavior for blocks with state
Synchronous SubsystemRepresent subsystem that has synchronous reset and enable behavior
Enabled Synchronous SubsystemRepresent enabled subsystem that has synchronous reset and enable behavior
Resettable Synchronous SubsystemRepresent resettable subsystem that has synchronous reset and enable behavior

Topics

Synchronous Subsystem Behavior with the State Control Block

What is a State Control Block and how does it generate cleaner HDL code

Generating HDL Code for Subsystems with Array of Buses

Generate HDL code for subsystems that use array of buses in the design.

Generate Reusable Code for Atomic Subsystems

Generate shared code for identical subsystems or subsystems identical except for their mask parameter values

Generate Parameterized Code for Referenced Models

Generate VHDL® generic or Verilog® parameter for model arguments in a model reference.

Generate HDL Code for Blocks Inside For Each Subsystem

An example that shows how to model and generate HDL code for blocks inside a For Each Subsystem.

Model Referencing for HDL Code Generation

Model referencing in your DUT subsystem enables you to:

Featured Examples