writeMemory

Write data to memory regions on FPGA or SoC hardware

Since R2023a

Syntax

writeMemory(hFPGA,addr,data)

writeMemory(hFPGA,InterfaceID,addr,data)

Description

writeMemory(hFPGA,addr,data) writes all words specified in data to the FPGA, hFPGA, starting from the address specified in addr and incrementing the address for each word. The address must be in the range of one of the AXI4 Slave or Memory interfaces added to the hFPGA object. The write operation writes to the corresponding interface based on the address provided.

writeMemory(hFPGA,InterfaceID,addr,data) writes all words specified in data to the FPGA, hFPGA, starting from the address specified in addr and incrementing the address for each word. The address must be in the range of one of the AXI4 Slave or Memory interfaces added to the hFPGA object. The write operation writes to the corresponding interface based on the InterfaceID provided.

Examples

Write Scalar Data to Memory

Write scalar data to FPGA-accessible memory.

Create an fpga object, hFPGA, for a Xilinx^® target.

hFPGA = fpga("Xilinx")

hFPGA = 

  fpga with properties:

       Vendor: "Xilinx"
   Interfaces: [0x0 fpgaio.interface.InterfaceBase]

    

Add the memory interface to the hFPGA object by using the addMemoryInterface function. Specify the memory interface name, base address, and address range. Save the memory interface object to hInterface.

hInterface = addMemoryInterface(hFPGA, InterfaceID = "myInterface",...
BaseAddress = 0x80000000,AddressRange = 0x20000000)

hInterface = 

  Memory with properties:

     InterfaceID: "myInterface"
     BaseAddress: "0x80000000"
    AddressRange: "0x20000000"
     WriteDriver: [1×1 matlabshared.libiio.sharedmem.write]
      ReadDriver: [1×1 matlabshared.libiio.sharedmem.read]
      InputPorts: [0×0 string]
     OutputPorts: [0×0 string]

Write data to a memory location.

writeMemory(hFPGA,0x80000000,uint32(5));

Write Vector Data to Memory

Write vector data to FPGA-accessible memory.

Create an fpga object, hFPGA, for a Xilinx target.

hFPGA = fpga("Xilinx")

hFPGA = 

  fpga with properties:

       Vendor: "Xilinx"
   Interfaces: [0x0 fpgaio.interface.InterfaceBase]

    

Add the memory interface to the hFPGA object by using the addMemoryInterface function. Specify the memory interface name, base address, and address range. Save the memory interface object to hInterface.

hInterface = addMemoryInterface(hFPGA, InterfaceID = "myInterface",...
BaseAddress = 0x80000000,AddressRange = 0x20000000)

hInterface = 

  Memory with properties:

     InterfaceID: "myInterface"
     BaseAddress: "0x80000000"
    AddressRange: "0x20000000"
     WriteDriver: [1×1 matlabshared.libiio.sharedmem.write]
      ReadDriver: [1×1 matlabshared.libiio.sharedmem.read]
      InputPorts: [0×0 string]
     OutputPorts: [0×0 string]

Write data to a memory location.

writeMemory(hFPGA,0x80000000,uint32(1:5));

Write to Overlapping Memory Locations

This example shows you how to use the optional InterfaceID argument to write data to a section of memory shared between multiple interfaces.

Create an fpga object, hFPGA, for a Xilinx target.

hFPGA = fpga("Xilinx")

hFPGA = 

  fpga with properties:

       Vendor: "Xilinx"
   Interfaces: [0x0 fpgaio.interface.InterfaceBase]

    

Add the AXI4 slave interface to the hFPGA object by using the addAXI4SlaveInterface function.

%% AXI4 Slave
addAXI4SlaveInterface(hFPGA, ...
	"InterfaceID", "EthernetAccess", ...
	"BaseAddress", 0x40D0000, ...
	"AddressRange", 0x10000);

Use the aximanager object to add a JTAG AXI Interface manager. Add the AXI4 slave interface to the hFPGA object by using the addAXI4SlaveInterface function.

axim = aximanager("Xilinx");
%% AXI4 Slave
addAXI4SlaveInterface(hFPGA, ...
	"InterfaceID", "JTAGAccess", ...
	"BaseAddress", 0x40D0000, ...
	"AddressRange", 0x10000,...
       "WriteDriver", axim,...
      "ReadDriver", axim,...
      "DriveAddressMode", "Full");

Write data to an overlapping memory location by using the preferred interface ID.

writeMemory(hFPGA, "EthernetAccess",...
0x400D0100, uint32(5));

Input Arguments

hFPGA — Target FPGA object

fpga object

Target FPGA object, specified as an fpga object.

addr — Starting address for write operation

nonnegative integer | nonnegative hexadecimal value

Starting address for the write operation, specified as a nonnegative integer that is a multiple of 4 or hexadecimal value that is a multiple of 4. The function casts the address to the uint32 or uint64 data type, depending on the memory interface address width. The address must be in the range of one of the AXI4 Slave or Memory interfaced added to the hFPGA object.

Example: 0x80000000 specifies a starting address of 0x80000000.

Data Types: uint32 | uint64

data — Data words to write

scalar | vector

Data words to write, specified as a uint32 scalar or vector. By default, the function writes the data to a contiguous address block and increments the address for each operation.

When you specify a large operation size, such as when you write a block of DDR memory, the function automatically breaks the operation into multiple bursts, using the maximum supported burst size of 256 words.

Example: [1:100] specifies 100 contiguous memory locations.

Data Types: uint32

InterfaceID — Name of FPGA interface

"" | string

Name of FPGA interface, specified as a string.

Version History

Introduced in R2023a