Check delay balancing setting
Check Balance Delays is enabled.
This check reports a warning if the Balance delays setting is disabled on the model. When you generate HDL code, certain optimizations or block implementations can introduce delays along some signal paths in your model. If Balance delays is disabled, the code generator does not introduce equivalent delays on other parallel signal paths, which can result in a numerical mismatch between the original model and the generated model.
Results and Recommended Actions
To fix this warning, click Modify Settings, and the code generator enables the Balance delays setting on the model. You can then rerun the check.