Specify the Clock Enable Rate

Why Specify the Clock Enable Rate?

When HDL Coder™ performs area optimizations, it might upsample parts of your design (DUT), and thereby introduce an increase in your required DUT clock frequency.

If the coder upsamples your design, it generates a message indicating the ratio between the new clock frequency and your original clock frequency. For example, the following message indicates that your design’s new required clock frequency is 4 times higher than the original frequency:

The design requires 4 times faster clock with respect to the base rate = 1

This frequency increase introduces a rate mismatch between your input clock enable and output clock enable, because the output clock enable runs at the slower original clock frequency.

With the Clock enable rate option, you can choose whether to drive the input clock enable at the faster rate (DUT base rate) or at a rate that is less than or equal to the original clock enable rate (Input data rate).

How to Specify the Clock Enable Rate

In the HDL Workflow Advisor, select MATLAB to HDL Workflow > Code Generation. Click the Clocks & Ports tab.

For the Clock enable rate option, select Input data rate or DUT base rate.

Clock enable rate Option Clock Enable Behavior

Clock enable rate Option	Clock Enable Behavior
Input data rate (default)	Each assertion of the input clock enable produces an output clock enable assertion. You can assert the input clock enable at a maximum rate of once every N clocks. N = the upsampled clock rate / original clock rate. For example, if you see the message, “`The design requires 4 times faster clock with respect to the base rate = 1`”, your maximum input clock enable rate is once every 4 clocks.
DUT base rate	Input clock enable rate does not match the output clock enable rate. You must assert the input clock enable with your input data N times to get 1 output clock enable assertion. N = the upsampled clock rate / original clock rate. For example, if you see the message, “`The design requires 4 times faster clock with respect to the base rate = 1`”, you must assert the input clock enable 4 times to get 1 output clock enable assertion.

Input data rate (default)

Each assertion of the input clock enable produces an output clock enable assertion.

You can assert the input clock enable at a maximum rate of once every N clocks. N = the upsampled clock rate / original clock rate.

For example, if you see the message, “The design requires 4 times faster clock with respect to the base rate = 1”, your maximum input clock enable rate is once every 4 clocks.

DUT base rate

Input clock enable rate does not match the output clock enable rate. You must assert the input clock enable with your input data N times to get 1 output clock enable assertion. N = the upsampled clock rate / original clock rate.

For example, if you see the message, “The design requires 4 times faster clock with respect to the base rate = 1”, you must assert the input clock enable 4 times to get 1 output clock enable assertion.