When you enable speed and area optimizations that insert pipeline registers, use the clock-rate pipelining optimization to identify multicycle paths in your design. Clock-rate pipelining inserts pipeline registers at the faster clock rate, which improves clock frequency without introducing additional latency or by adding minimal latency. You can use clock-rate pipelining with a Simulink® model or a MATLAB® function.
Rationale for Clock-Rate Pipelining
HDL Coder™ introduces pipelines when you specify certain block implementations or enable some optimizations on the Simulink model or MATLAB function, such as:
Multi-cycle block implementations
Input and output pipelining
Floating-point library mapping
Native floating-point HDL code generation
By default, in slow paths, these pipeline registers operate at the slow data rate. When you enable clock-rate pipelining, the pipeline registers operate at the faster clock rate. Clock-rate pipelining does not affect existing design delays in your model. It is an alternative to using multicycle path constraints with your synthesis tool.
How Clock-Rate Pipelining Works in a Simulink Model
The clock-rate pipelining optimization identifies slow paths or regions in the model by analyzing the block sample times. Blocks that have a sample time greater than the device under test (DUT) base sample time are part of the slow path, and are potential candidates for clock-rate pipelining. In these slow paths, HDL Coder enables optimizations to introduce pipeline delays at the clock rate.
If you specify an Oversampling factor greater than one, the DUT sample time becomes slower than the actual clock rate. HDL Coder determines the maximum number of clock-rate pipelines that it can insert based on the DUT-to-block sample time ratio and the oversampling factor.
Maximum number of clock-rate delays = (block_rate
÷ DUT_base_rate) ×
Clock-rate pipelining identifies regions in the model that have the same slow data rate, and are delimited by either Delay blocks or blocks that introduce a rate transition. HDL Coder converts these regions to the faster clock rate by introducing Repeat blocks at the input of the region and Rate Transition blocks at the output of the region. If the output of a clock-rate region is a Delay block at the data rate, HDL Coder absorbs that Delay block. To accommodate the delay, HDL Coder introduces several clock-rate pipelines corresponding to the ratio of the data rate to the clock rate.
HDL Coder generates a script that highlights blocks in your model that are
obstacles to clock-rate pipelining and a script to clear the highlighting.
Sometimes, if HDL Coder is unable to implement resource sharing or streaming at the clock
rate, it displays a code generation error with a recommendation for changing the
Oversampling value. To clear highlighting, click the
clearhighlighting script in the MATLAB Command Window.
How Clock-Rate Pipelining Works in a MATLAB Function
A MATLAB function, which is the DUT when generating HDL code from MATLAB, runs at a single data rate. If you want a clock rate that is faster than the data rate, you can use clock-rate pipelining. You specify how much faster you want your clock rate to be than the DUT data rate by specifying an oversampling factor greater than one. The maximum number of clock-rate delays that HDL Coder can insert is equal to the oversampling factor.
You can also use clock-rate pipelining to optimize speed if you have other code generation options that introduce latency in a feedback loop, such as the use of persistent variables or native floating point.
Clock-Rate Pipelining and Hierarchy Flattening
You can use the clock-rate pipelining optimization with or without flattening the subsystem hierarchy. Flatten the subsystem hierarchy when you want to maximize opportunities for sharing resources in your design. To flatten the subsystem hierarchy, enable FlattenHierarchy on the top-level Subsystem. By default, all Subsystem blocks inside the top-level subsystem inherit this FlattenHierarchy setting. Hierarchy flattening brings several clock-rate regions to the same level in the hierarchy and combines them, which increases opportunities for clock-rate pipelining. However, it breaks the modularity of your design and affects the readability of the generated HDL code. See also Hierarchy Flattening.
To apply clock-rate pipelining without flattening the hierarchy, on the top-level subsystem in your model, disable FlattenHierarchy. If your design uses fixed-point data types, enable some optimizations on the underlying subsystems. In this case, HDL Coder introduces clock-rate pipelines in your design while preserving the subsystem hierarchy, which:
Improves the modularity of your design and makes navigation through the generated model easier especially in large designs with complex hierarchies.
Improves readability of the generated HDL code by creating multiple Verilog or VHDL files for the various Subsystem blocks in your design.
Clock-Rate Pipelining for DUT Output Ports
To produce DUT outputs as soon as possible by passing the outputs from the DUT at
the clock rate rather than the data rate, select the Allow clock-rate
pipelining of DUT output ports configuration parameter or use the
ClockRatePipelineOutputPorts property. This property
changes the timing of your DUT interface by changing the sample time of the DUT
output ports from a slower data rate to the clock rate. To adjust for the difference
in timing, HDL Coder generates messages that provide the phase offset of each output port.
For example, this message means that the output data from
portname is valid after 31 clock cycles:
Phase of output port To set this parameter, see Allow clock-rate pipelining of DUT output ports.
The validation model adjusts for the timing difference by inserting a Rate Transition block at the DUT output and comparing the output of the Rate Transition block with the original output. The RTL test bench logs the output data at the input of the Rate Transition block and compares it with the DUT output in the RTL simulation.
When producing DUT outputs at the clock rate, the outputs are ready as soon as
possible, even if one output is ready before another. For example, this is useful if
you run a hardware-in-the-loop simulation with a control system and have a plant
model running at a slow rate and discrete logic such as control signals in the DUT
that need to run at a faster rate or with a short response delay time. To
synchronize the outputs while still satisfying the highest-latency requirements of
the outputs, you can balance clock-rate pipelined DUT output ports by selecting the
Balance clock-rate pipelined DUT output ports
configuration parameter or using the
BalanceClockRateOutputPorts property. You can apply this
property when interfacing your logic with a valid signal interface to align the
output of your logic path and the output of the valid signal path. To set this
parameter, see Balance clock-rate pipelined DUT output ports.
Specify Clock-Rate Pipelining
You can generate HDL code with the clock-rate pipelining optimization from a Simulink model or MATLAB function.
Specify Clock-Rate Pipelining for a Simulink Model
You can set clock-rate pipelining on a model or, for finer control, on subsystems within the top-level DUT subsystem. By default, clock-rate pipelining is enabled on the model. To disable clock-rate pipelining from the UI:
In the Apps tab, select HDL Coder. The HDL Code tab appears.
Click Settings. In the HDL Code Generation > Optimization > Pipelining tab, clear Clock-rate pipelining and click OK.
At the command line, use the
hdlset_param function to set the
ClockRatePipelining property to
You can use clock-rate pipelining for a subsystem within the top-level DUT
subsystem. To model a control path in your design at the data rate instead of
the clock rate, put the control path in a subsystem, and disable clock-rate
pipelining for that subsystem. To disable clock-rate pipelining for a subsystem
within the top-level DUT subsystem, set ClockRatePipelining
off for that subsystem. See also Set Clock-Rate Pipelining For a Subsystem.
Specify Clock-Rate Pipelining for a MATLAB Function
To enable the clock-rate pipelining for a MATLAB function:
Open the MATLAB HDL Workflow Advisor. To get started with the MATLAB HDL Workflow Advisor, see Basic HDL Code Generation and FPGA Synthesis from MATLAB.
In the left pane, click the HDL Code Generation task. In the right pane, navigate to the Optimization tab and select Clock Rate Pipelining.
Click the Clocks & Ports tab and set Oversampling factor to a value greater than one.
Limitations for Clock-Rate Pipelining
These blocks inhibit clock-rate pipelining, and therefore delimit clock-rate pipelining regions:
Discrete PID Controller
Dual Port RAM
Dual Rate Dual Port RAM
FFT HDL Optimized
HDL Minimum Resource FFT
HDL Streaming FFT
MATLAB System, if it uses persistent variables
Reusable Subsystem, if
FlattenHierarchyis not enabled
Simple Dual Port RAM
Single Port RAM
HDL Coder does not support clock-rate pipelining for:
Black box subsystem or black box model reference blocks.
Subsystems that contain blocks not supported for clock-rate pipelining.
Altera DSP Builder subsystems.
Xilinx System Generator subsystems
Communications Toolbox™ blocks.
DSP System Toolbox™ blocks, except for Delay and Discrete FIR Filter.
HDL Coder does not support applying both the streaming and sharing optimizations on the same resource when you use the clock-rate pipelining optimization. Either disable clock-rate pipelining or use either the streaming optimization or the sharing optimization on the same resource when clock-rate pipelining is enabled.
HDL Coder does not support clock-rate pipelining when Clock
inputs is set to
- Increase Clock Frequency Using Clock-Rate Pipelining
- Optimize Feedback Loop Design and Maintain High Data Precision for HDL Code Generation