Using the HDL Workflow Advisor, you can generate a custom IP core from a model or algorithm. The generated IP core is sharable and reusable. You can integrate it with a larger design by adding it in an embedded system integration environment, such as Intel® Qsys, Xilinx® EDK, or Xilinx IP Integrator.
To learn how to generate a custom IP core, see:
You can generate an IP core:
With an AXI4 or AXI4-Lite interface.
With an AXI4 or AXI4-Lite interface and AXI4-Stream Video interfaces.
Without any AXI4 or AXI4-Lite interfaces. To learn more, see Generate Board-Independent HDL IP Core from Simulink Model.
The Algorithm from MATLAB/Simulink block represents your DUT. HDL Coder™ generates the rest of the IP core based on your target platform interface settings and processor/FPGA synchronization mode.
You can map each port in your DUT to one of the following target platform interfaces in the IP core:
AXI4-Lite: Use this slave interface to access control registers or for lightweight data transfer. HDL Coder generates memory-mapped registers and allocates address offsets for the ports you map to this interface.
AXI4: Use this slave interface to connect to components that support burst data transmission. HDL Coder generates memory-mapped registers and allocates address offsets for the ports you map to this interface.
Interfaces AXI4 and AXI4-Lite are also referred to as AXI4 slave interfaces. In the generated HDL IP core, you can have either AXI4 or AXI4-Lite interface but not both interfaces.
AXI4-Stream Video: Use this interface to send or receive a 32-bit scalar video data stream.
External ports: Use external ports to connect to FPGA external IO pins, or to other IP cores with external ports.
FPGA Data Capture - JTAG: Use FPGA Data Capture over the JTAG interface to observe test point signals and signals at the DUT output ports while your design runs on the FPGA. For an example of marking internal signals as test points, see Debug IP Core Using FPGA Data Capture. For more information on capturing data, see Data Capture Workflow (HDL Verifier).
To use this interface, you must download a hardware support package for your FPGA board. See Download FPGA Board Support Package (HDL Verifier).
To learn more about the AXI4, AXI4-Lite and AXI4-Stream Video protocols, refer to your target hardware documentation.
HDL Coder generates synchronization logic in the IP core based on the processor/FPGA synchronization mode you choose.
When generating a custom IP core, the following processor/FPGA synchronization options are available:
Free running (default)
Coprocessing – blocking
To learn more about the processor/FPGA synchronization modes, see Processor and FPGA Synchronization.
After you generate a custom IP core, the IP core files are in the
ipcore folder within your project folder. In the HDL Workflow
Advisor, you can view the IP core folder name in the IP core folder
field of the HDL Code Generation > Generate RTL Code and IP Core task.
The IP core folder contains the following generated files:
IP core definition files.
HDL source files (.vhd or .v).
A C header file with the register address map.
(Optional) An HTML report with instructions for using the core and integrating the IP core in your embedded system project.
IP Core Generation workflow does not support :
RAM Architecture set to
Generic RAM without
Using different clocks for the IP core and the AXI interface. The
AXILite_ACLK must be
synchronous and connected to the same clock source. The
be connected to the same reset source. See Synchronization of Global Reset Signal to IP Core Clock Domain.