HDL Coder™ native floating-point technology can generate HDL code from your floating-point design. These are some of the key features:
Generation of target-independent HDL code that you can deploy on any FPGA or ASIC.
Support for the full range of IEEE-754 features including denormal numbers, exceptions, and rounding modes.
Extensive support for math and trigonometric blocks.
You can follow these guidelines as best practices when modeling your design for native floating-point code generation.
Each guideline has a severity level that indicates the level of compliance requirements. To learn more, see HDL Modeling Guidelines Severity Levels.
Native floating-point support in HDL Coder generates code from your floating-point design. If your design has complex math and trigonometric operations or has data with a large dynamic range, use native floating-point. The generated HDL code is target-independent and complies with the IEEE-754 standard of floating-point arithmetic. To learn more, see Getting Started with HDL Coder Native Floating-Point Support.
You can use these modeling guidelines when using the native floating-point support in HDL Coder.
The HDL Floating Point Operations block library consists
of math and trigonometric functions and certain Simulink blocks that are
configured for HDL code generation in native floating-point mode. For example,
Discrete FIR Filter with Architecture
You can generate HDL code for models that contain floating-point and fixed-point data types in native floating-point mode. Floating point types have higher dynamic range but can potentially occupy more area on the target hardware. To design for these trade-offs, in your Simulink® model, it is recommended to use floating-point data types to model the algorithm data path and fixed-point types to model the control logic. To switch between floating-point and fixed-point data types, use Data Type Conversion blocks.
See also Data Type Considerations.
By enabling optimizations on the model, you can improve area and timing of your design on the target FPGA device. For example, to save area on the target FPGA device, use the resource sharing optimization. To share:
See also Resource Sharing.
Floating-point designs have an inherent latency by default. This latency is added when generating HDL code for your model. It is recommended that you simulate latency in your model by adding this latency information to your original Simulink model. The code generator absorbs this latency during HDL code generation. To learn more, see Latency Values of Floating-Point Operators.
You can customize the latency of an entire model, or selectively for certain blocks in your design. Using custom settings, you can specify a custom latency and design for trade-offs between latency and throughput.
To learn more, see Latency Considerations with Native Floating Point.
Certain modeling patterns that you use can optimize your model when you
generate code with native floating-point technology. For example, if you are
computing the trigonometric sine and cosine of the same input, in the
HDL Floating Point Operations block library, use the
Sincos block instead of separate Sin and
Cos blocks. The Sincos block shares some of
the logic that is used for computing the sine and cosine of the input. This
implementation reduces the area footprint on the target FPGA device.
See also Trigonometric Function.
To obtain a lower latency implementation, use
as the HDL Architecture for blocks such as the Sum
of Elements and Product of Elements.