Synthesis Attributes in HDL Code Generation

Since R2026a

Synthesis attributes are special directives embedded in HDL code that guide synthesis tools during hardware implementation. These attributes do not affect simulation behavior, but they are essential for optimizing and mapping the design to hardware. You can use them to control resource sharing, improve timing performance, manage area and power trade-offs, and guide placement and routing decisions.

You can add custom synthesis attributes to the generated HDL code for blocks or block outputs by using either the HDL Block Properties dialog box or the command-line interface. The syntax and behavior of synthesis attributes may vary depending on the synthesis tool, but they are independent of the target HDL language.

For more information about setting synthesis attributes and generating HDL code, see these examples:

• To set synthesis attributes programmatically, see Configure Custom Synthesis Attributes for Simulink Blocks.

• To set synthesis attributes interactively, see Use Synthesis Attributes to Map Adders to DSPs on FPGAs.

This table lists sample synthesis attributes that various synthesis tools support. Attribute availability and naming may vary depending on the synthesis tool version and device family.

Synthesis Tool	Attribute Name	Attribute Value(s)	Description
Xilinx® Vivado®	ram_style	block| distributed| registers| ultra	Specifies RAM implementation style.
	use_dsp	yes| no	Forces use of DSP blocks for arithmetic operations.
	critical_sig_opt	true| false	Marks a signal for critical path optimization
	dsp_folding	true| false	Enables DSP folding optimization.
	cascade_height	Positive integer	Specifies the number of cascaded DSP blocks.
	dont_touch	true| false	Prevents synthesis from optimizing or removing the marked object.
	black_box	true| false	Treats a module as a black box during synthesis.
	keep	true | false	Prevents removal or merging of the marked signal or module.
	fsm_encoding	one-hot| binary| gray	Specifies encoding style for finite state machines.
	max_fanout	Positive integer	Limits the fanout of a signal.
Intel® Quartus®	enum_encoding	one-hot| binary| gray	Specifies logic encoding for an enumeration type.
	keep	true| false	Prevents removal of a net during optimization.
	maxfan	Positive integer	Limits fan-out of a register.
	ramstyle	logic| M9K| M10K| M20K| M144K| MLAB	Specifies RAM block type for inferred RAM.
	multstyle	auto| logic| DSP	Specifies multiplication implementation style.
Microchip Libero®	loop_limit	Positive integer	Sets iteration limit for for-loops.
	syn_preserve	true| false	Preserves registers that might be optimized away.
	syn_keep	true| false	Prevents removal of internal signals.
	syn_black_box	true| false	Treats module as black box.
	syn_enum_encoding	binary| one-hot| gray	Specifies FSM encoding style.
	syn_hier	soft| hard	Controls hierarchy flattening.
	syn_ramstyle	block_ram| registers| lsram| uram	Specifies RAM implementation style.
	syn_multstyle	logic| block_mult	Specifies multiplier implementation style.