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FPGA Data Capture

Capture signal data from live FPGA

Use FPGA data capture to observe signals from your design while the design is running on the FPGA. This feature captures a window of signal data from the FPGA and returns the data to MATLAB® or Simulink®. To capture the signals, HDL Verifier™ generates an IP core that you must integrate into your HDL project and deploy to the FPGA along with the rest of your design. HDL Verifier also generates an app, System object™, and Simulink model that communicate with the FPGA and return the data to MATLAB or Simulink.

To capture FPGA data:

  1. Generate customized components and an IP core. Specify port names and sizes for the generated IP. These ports connect to the signals you want to capture, and the signals you want to use as triggers to control when the capture occurs.

  2. Integrate the generated IP into your FPGA design and deploy the design to your FPGA board. This step is automated when using HDL Workflow Advisor.

  3. Use the generated app, System object, or Simulink model to capture data for analysis, verification, or display. You can configure a trigger condition to control when the capture occurs and a capture condition to control which data to capture.

For a Xilinx® FPGA board over a JTAG connection, you can capture data from different clock domains to debug your FPGA design by using multiple FPGA data capture IPs. For more information about multiple FPGA data capture, see Capture Asynchronous Data.

To use FPGA data capture, you must download a hardware support package for your FPGA board. See documentation for support packages. For an Intel® FPGA board, see FPGA Data Capture. For a Xilinx FPGA board, see FPGA Data Capture.

For information on downloading support packages, see Download FPGA Board Support Package.


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Data Capture Requirements and Preparation