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SystemVerilog DPI Pane

SystemVerilog DPI Overview

Specify options for exporting a Simulink® algorithm (model or subsystem) with a DPI interface for Verilog® or SystemVerilog Simulation. You can wrap generated C code with a DPI wrapper that communicates with a SystemVerilog thin interface function in a SystemVerilog simulation.

This feature is available in the Model Configuration Parameters dialog. You must have an Embedded Coder® license to use this feature.

To get help on an option

  1. Right-click the option's text label.

  2. Select What's This from the popup menu.

Customize SystemVerilog generated code

Indicate that you want to customize the generated SystemVerilog code.

Settings

Default: Off

On

Customize generated SystemVerilog code

Off

Do not customize generated SystemVerilog code

Dependencies

You must enter a template file in Source file template: if you want the generator to include customized code.

Source file template:

Specify the file name and location of the template you want to use for customizing the generated SystemVerilog code. You may use one of the templates supplied by HDL Verifier™, or you may specify your own template file with the following conditions:

  • The file must be on MATLAB® path and be searchable.

  • The file must have a .vgt extension.

Report run-time error

Select this parameter to export run-time errors from a Simulink execution to the DPI and UVM simulation environment.

Severity

Select the severity for run-time errors.

Default: Fatal

Info

Set the run-time error to a `uvm_info macro for UVM components or a $display statement for DPI components.

Warning

Set the run-time error to a `uvm_warning macro for UVM components or a $warning statement for DPI components.

Error

Set the run-time error to a `uvm_error macro for UVM components or a $error statement for DPI components.

Fatal

Set the run-time error to a `uvm_fatal macro for UVM components or a $fatal statement for DPI components.

Dependencies

To enable this parameter, select Report run-time error.

Testbench Generation

Indicate that you want to generate a testbench for the DPI component.

Settings

Default: Off

On

Create a testbench for the generated DPI component. This testbench checks that the generated DPI or UVM artifacts are functionally equivalent to the Simulink model.

Off

Do not create a testbench for the generated DPI component

HDL simulator

Select the HDL simulator to use when simulating the testbench in MATLAB

Default: Siemens Questa/ModelSim

Siemens Questa/ModelSim

Set the HDL simulator to Siemens® Questa™ or ModelSim™.

Cadence Xcelium

Set the HDL simulator to Cadence® Xcelium™.

Synopsys VCS

Set the HDL simulator to Synopsys® VCS®.

Vivado Simulator

Set the HDL simulator to AMD® Vivado®.

Test point access

Select the type of test point access functions to generate in the SystemVerilog DPI component.

Settings

Default: None

None

The tool does not generate test point access functions.

One function per Test Point

The component includes a separate access function for each signal.

DPI_Name_TestPoint(input chandle objhandle,inout real Name);
One function for all Test Points

The component includes a single access function that returns values for all test points.

DPI_TestPointAccessFcn(input chandle objhandle,input real Name1,inout real Name2);

Ports data type

Select the SystemVerilog data type that will be used for ports that have fixed-point data.

Settings

Default: Compatible C Type

Compatible C Type

Generate a compatible C Type interface for the port.

Bit Vector

Generate a Bit Vector Type interface for the port.

Logic Vector

Generate a Logic Vector Type interface for the port.

Connection

Select how signals are connected when the module is instantiated.

Settings

Default: Port list

Port list

Generate a SystemVerilog module with a port list in the header, representing its interface.

Interface

Generate a SystemVerilog interface, and a module using that interface.

Composite Data Type

Choose how the SystemVerilog ports are generated when your Simulink model includes a port which is a Nonvirtual bus or a complex data type. Choose between interfaces with struct data types or flattened SystemVerilog ports.

Settings

Default: Flattened

Flattened

Generate a SystemVerilog module with flattened ports.

Structure

Generate a SystemVerilog module with struct data type ports.

Scalarize matrix and vector ports

Choose how the SystemVerilog ports are generated when your Simulink model includes a port which is an array or matrix data type.

When selecting this box, each element in the array or matrix creates a scalar port in the generated SystemVerilog.

When clearing this box, the generated SystemVerilog ports preserve the array or matrix as defined in Simulink.

Component template type

Select a template for SystemVerilog DPI generation.

  • Sequential – Creates a registered design, with a clock and reset port. This option is the default.

  • Combinational – Creates a combinational design, with no clock and reset ports. When selecting this option, the outputs immediately reflect changes in the inputs.

  • UVM Sequence – Creates a UVM sequence DPI component, a sequencer, and a sequence transaction.

  • UVM Predictor – Creates a UVM predictor DPI component, a predictor configuration object, input and output transaction types.

  • UVM Scoreboard – Creates a UVM scoreboard DPI component, a scoreboard transaction, input and output transaction types, and a scoreboard configuration object.
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