Use Variable-Sized Vectors in SystemVerilog DPI Component

R2026b

This example uses:

This example shows how to configure, generate, and use a SystemVerilog DPI (SVDPI) component with variable-length inputs or outputs.

Design Task

When you generate an SVDPI from a MATLAB® function that includes a variable-sized vector input or output, the result is a SystemVerilog module with a variable-sized input or output.

When you use variable-size numeric ports - it generates open arrays in SystemVerilog.
When you use variable-size character vectors - it generates strings in SystemVerilog.

Follow this example to configure, generate, and use the component in a SystemVerilog environment.

MATLAB Function

This example uses the function varSizeVectorSupport, a sine function where the size of the input vec is variable. The output of the function is derived from the input, and therefore the output size is also variable. The function also has an input port that holds a label, specified as a character vector, and output label.

Testbench

Use the provided varSizeVectorSupport_tb testbench to stimulate the function with fixed-sized signals. Then, generate a SystemVerilog testbench to test the generated SystemVerilog module. You can later change the port sizes of the generated SystemVerilog testbench (or write a new testbench) without regenerating a DPI module from the varSizeVectorSupport function.

Configure Generation Options

Create an svdpiConfiguration object for a sequential module with variable-size ports. Then, set the toolchain to a supported simulator (for example, the Questa™ simulator). Make sure that the specified simulator is on the system path.

cfg = svdpiConfiguration('sequential-module-varsize');
if ispc
    cfg.CoderConfiguration.Toolchain = "Siemens Questa/Modelsim (64-bit Windows)";
else
    cfg.CoderConfiguration.Toolchain = "Siemens Questa/Modelsim (64-bit Linux)";
end

Generate SystemVerilog DPI Component

To generate the SystemVerilog module, use the dpigen function.

You must pass the configuration object to the dpigen function using the -config argument.
Use the -args argument to specify the size of the generated ports. To set an upper bound value for the variable-length vector, specify that value in the coder.Type object. For example, to set an upper bound of 20 for vec, enter this code at the MATLAB command prompt.

dpigen -config cfg varSizeVectorSupport -args {coder.typeof(1,[1 20],[0 1]),1,1,coder.typeof('c',[1 20],[0 1])}

### Generating DPI-C Wrapper varSizeVectorSupport_dpi.c
### Generating DPI-C Wrapper header file varSizeVectorSupport_dpi.h
### Generating file varSizeVectorSupport_pkg.sv
### Generating file varSizeVectorSupport.sv
### Generating vsim makefile/script varSizeVectorSupport.do
Code generation successful.

### Compiling DPI library using HDL toolchain 'vsim'
### Successful script execution.

Use inf to specify that the port size is of variable-length and unbounded in the generated SystemVerilog.
To generate a SystemVerilog testbench from a MATLAB testbench function, use the -testbench argument.

dpigen -config cfg varSizeVectorSupport -testbench varSizeVectorSupport_tb -args {coder.typeof(1,[1 inf],[0 1]),1,1,coder.typeof('c',[1 20],[0 1])}

### Generating DPI-C Wrapper varSizeVectorSupport_dpi.c
### Generating DPI-C Wrapper header file varSizeVectorSupport_dpi.h
### Generating file varSizeVectorSupport_pkg.sv
### Generating file varSizeVectorSupport.sv
### Generating vsim makefile/script varSizeVectorSupport.do
### Running simulation to capture input and expected outputs for a standalone testbench.
### This may take some time...
Code generation successful.

### ...DONE with test-vector capture.
### Generating file run_tb_mq.do
### Generating file varSizeVectorSupport_tb.sv
Code generation successful.

### Compiling DPI library using HDL toolchain 'vsim'
### Successful script execution.

Generated Interface

Because vec is specified as a variable-sized vector during code generation in this example, the generated SystemVerilog includes the variable-sized input vec and output y. The data type of the output y is derived from the input data type. These variable-sized ports are declared as SystemVerilog open arrays ([ ]).

Note that the character vectors label and outLabel are defined as strings in this interface.

This code shows the generated interface for the varSizeVectorSupport function.

interface varSizeVectorSupport_interface;
  bit clk  ;
  bit clk_enable  ;
  bit reset  ;
  real vec [];
  real amp  ;
  real freq  ;
  string label ;
  shortint y [];
  string outLabel ;
endinterface

Simulate in Questa Simulator

To simulate the testbench and verify the generated component, run the following command:

cd codegen/dll/varSizeVectorSupport/dpi_tb
!vsim -c -do run_tb_mq.do

Reading pref.tcl 
 
# 2025.3 
 
# do run_tb_mq.do 
# run -all 
# .. 
# ** Warning: (vlib-34) Library already exists at "work". 
# Errors: 0, Warnings: 1 
# QuestaSim-64 vlog 2025.3 Compiler 2025.09 Sep 15 2025 
# Start time: 13:43:15 on Apr 07,2026 
# vlog "+define+MG_SIM" ../varSizeVectorSupport_pkg.sv ../varSizeVectorSupport.sv ./varSizeVectorSupport_tb.sv  
# ** Note: (vlog-220) 'D:/share/apps/HDLTools/ModelSim/questasim-2025.3/win64/win64/../modelsim.ini' is used as the ini file. 
# -- Compiling package varSizeVectorSupport_pkg 
# -- Compiling package varSizeVectorSupport_sv_unit 
# -- Importing package varSizeVectorSupport_pkg 
# -- Compiling interface varSizeVectorSupport_interface 
# -- Compiling module varSizeVectorSupport 
# -- Compiling package varSizeVectorSupport_tb_sv_unit 
# -- Compiling module varSizeVectorSupport_tb 
#  
# Top level modules: 
# 	varSizeVectorSupport_tb 
# End time: 13:43:16 on Apr 07,2026, Elapsed time: 0:00:01 
# Errors: 0, Warnings: 0 
# ** Note: (vsim-220) 'D:/share/apps/HDLTools/ModelSim/questasim-2025.3/win64/win64/../modelsim.ini' is used as the ini file. 
# vsim -c -voptargs="+acc" -L ../work work.varSizeVectorSupport_tb  
# Start time: 13:43:17 on Apr 07,2026 
# ** Note: (vsim-8009) Loading existing optimized design _opt 
# //  Questa Sim-64 
# //  Version 2025.3 win64 Sep 15 2025 
# // 
# // Unpublished work. Copyright 2025 Siemens 
# // 
# // This material contains trade secrets or otherwise confidential information 
# // owned by Siemens Industry Software Inc. or its affiliates (collectively, 
# // "SISW"), or its licensors. Access to and use of this information is strictly 
# // limited as set forth in the Customer's applicable agreements with SISW. 
# // 
# // This material may not be copied, distributed, or otherwise disclosed outside 
# // of the Customer's facilities without the express written permission of SISW, 
# // and may not be used in any way not expressly authorized by SISW. 
# // 
# Loading sv_std.std 
# Loading work.varSizeVectorSupport_pkg(fast) 
# Loading work.varSizeVectorSupport_tb_sv_unit(fast) 
# Loading work.varSizeVectorSupport_tb(fast) 
# Loading work.varSizeVectorSupport_sv_unit(fast) 
# Loading work.varSizeVectorSupport_interface(fast__1) 
# Loading work.varSizeVectorSupport(fast) 
# Loading C:/Users/user/AppData/Local/Temp\hagam@MATHWORKS-GSCFO_dpi_44436\win64_gcc-7.4.0\vsim_auto_compile.dll 
# Tolerance parameter for floating point comparisons is set to: 4.440892e-16. 
# Override the SystemVerilog parameter using the EXTRA_SVDPI_SIM_ARGS or EXTRA_SVDPI_COMP_ARGS appropriate for your simulator. 
# **************TEST COMPLETED (PASSED)************** 
# ** Note: $finish    : ./varSizeVectorSupport_tb.sv(143) 
#    Time: 52 ns  Iteration: 0  Instance: /varSizeVectorSupport_tb 
# Vector compare count = 2 
# End time: 13:43:21 on Apr 07,2026, Elapsed time: 0:00:04 
# Errors: 0, Warnings: 0

Limitations

This feature does not support:

Variable-sized matrices on the interface. If you have a matrix in your model, convert it to a variable-sized vector before connecting to an input or output.
Structure data types with fields of variable size
Variable-sized arrays of structures
Cross-platform DPI component generation