This example is the first part of a two-part series to help you develop a Monopulse Technique where the signal is down converted via digital down conversion(DDC). The model designed here is suitable for implementation on FPGA. This example focuses on the design of monopulse technique to estimate the azimuth and elevation of an object. The second part of the example FPGA Based Monopulse Technique Workflow: Part 2 - Code Generation shows how to generate HDL code from the implementation model and verify that the generated HDL code produces the correct results compared to the behavioral model. The model is implementation ready and this will be verified in the example. The entire workflow is designed in fixed-point.
The example shows how to design an FPGA implementation-ready monopulse technique to match a corresponding behavioral model in Simulink® using the Phased Array System Toolbox™, DSP System Toolbox™, and Fixed-Point Designer™. To verify the implementation model, it compares the simulation output of the implementation model with the output of the behavioral model.
The Phased Array System Toolbox provides the floating-point behavioral model for the monopulse technique via a phased.MonopulseFeed System object. DSP System Toolbox provides the FIR filter essential for the down conversion filtering.
Fixed-Point Designer provides data types and tools for developing fixed-point and single-precision algorithms to optimize performance on embedded hardware. Bit-true simulations can be performed to observe the impact of limited range and precision without implementing the design on hardware.
Monopulse is a technique where the received echoes from different elements of an antenna are used to estimate the direction of arrival (DOA) of a signal. This in turn helps estimate the location of an object. The example uses DSP System Toolbox and Fixed-Point Designer to design the module. This technique utilizes four beams which help measure the angular position of the target. All the four beams are generated simultaneously and the difference of azimuth and elevation is achieved in a single pulse hence, the name monopulse.
The algorithm is implemented by utilizing Simulink® blocks that are HDL compatible. The model shown below assumes that the signal is received from the 4-element uniform rectangular array (URA). Hence the starting point for the model shows 4 sinusoids as inputs. Assuming a 4-element URA, the model is comprised of 4 receive channels from each of the elements of the URA. Once the signals are converted to the digital domain, DDC blocks will ensure that the frequency of the received signal is lowered therefore reducing the sample rate for processing. The block diagram below shows the subsystem which consists of the following modules.
Multi-Channel Input Signal
Monopulse Sum and Difference Channels
Below is the command to open the Simulink model
modelname = 'SimulinkDDCMonopulseHDLWorkflowExample'; open_system(modelname); % Ensure model is visible and not obstructed by scopes. open_system(modelname); set(allchild(0),'Visible','off');
The Simulink model has two branches. The top branch is the behavioral, floating-point model of the monopulse technique and digital down conversion chain algorithm and the bottom branch is the functionally equivalent fixed-point version using blocks that support HDL code generation. Apart from plotting the output of both branches to compare the two, the difference, or error, between sum channel of both the outputs has also been calculated and plotted.
Notice that there's a delay () at the output of the behavioral model. This is necessary because the implementation algorithm uses 220 delays to enable pipelining which creates latency that needs to be accounted for. This latency is necessary to time-align the output between the behavioral model and the implementation model.
The subsystem below shows how the received signal at sampled at 80 MHz and nearly 15 MHz carrier frequency is down-converted to baseband via the DDC and then passed on to the monopulse sum and difference subsystem. A DDC module is a combination of a numerically controlled oscillator (NCO) and a set of low-pass filters. NCO provides the signal to mix and demodulate the incoming signal. Open the subsystem that performs the down-conversion
open_system([modelname '/DDC and Monopulse HDL']);
Notice that a delay of 215 ms has been added to the sum and difference output of the steering vectors in the implementation subsystem to compensate for the delay that arises out of the down conversion chain.
A DDC also contains a set of low-pass filters as shown in the figure. Once mixed, the low-pass filtering of the mixed signal is required to eliminate the high frequency components. In this example, we use a cascaded filter chain to achieve the low-pass filtering. The NCO is used to generate the high accuracy sinusoid for the mixer. A latency of 6 is provided to the HDL-optimized NCO block. This signal is mixed with the incoming signal and is converted from a higher frequency to a relatively lower frequency as it progresses through the various stages.
open_system([modelname '/DDC and Monopulse HDL/HDL_DDC']);
In this example, the incoming signal has a carrier frequency of 15 MHz and is sampled at 80 MHz . The down-conversion process brings the sampled signal down to a few kHz. The coefficients for relevant low-pass FIR filters are designed using filterBuilder, one of which is as described below. The values must be chosen to satisfy the required pass-band criteria.
Once generated, the coefficients can be exported to the HDL optimized FIR Filter block.
Apart from generating down-converted signal, another aspect for consideration for monopulse is the steering vector for different elements. The steering vectors have been generated for an incident angle of azimuth 30 degrees and elevation 20 degrees. The steering vectors are passed on to the digital comparator to provide the desired sum and difference channel outputs. The down-converted signal is then multiplied by the conjugate of these vectors as shown in the figure below. By processing the sum and difference channels, the DOA of the received signal can be found. The digital comparator that compares the steering vectors for the different elements of the antenna array can be seen by:
open_system([modelname '/DDC and Monopulse HDL/DIGITAL COMPARATOR']);
In the figure above, the digital comparator takes the steering vectors and computes the sum and difference of the different steering vectors sVA, sVB, sVC and sVD respectively. You can also calculate the steering vectors by using the phased.SteeringVector System object or you can generate them using method similar to the one shown in the FPGA Based Beamforming in Simulink: Part 1 - Algorithm Design. Once the sum and difference of various steering vectors corresponding to each element of the array has been done, the calculation of sum and difference channels for corresponding azimuth and elevation angles are performed. From the Sum and Difference Monopulse subsystem, 3 signals are obtained, namely the sum, the azimuth difference, and the elevation difference. The entire arithmetic is performed in fixed point. The monopulse sum and difference channel subsystem can be opened by using the command below
open_system([modelname '/DDC and Monopulse HDL/Monopulse Sum and Difference Channel']);
To compare results of the implementation model to the behavioral model, run the model created to display the results. You can run the Simulink model by clicking the Play button or calling the sim command on the MATLAB command line as shown below. Use Scope blocks to compare the output frames.
The plots show the output from sum and difference channels. These channels can be fed to an estimator to indicate the angle/direction of the object.
This example demonstrates how to design an FPGA implementation-ready algorithm, automatically generate HDL code, and verify the HDL code in Simulink. The example illustrates the design of a Simulink model for a DDC and monopulse feed system, verify the results with an equivalent behavioral setup from the Phased Array System Toolbox that provides the golden reference. Apart from the behavioral model, the example demonstrates how to create a subsystem for implementation using Simulink blocks that support HDL code generation. It also compared the output of the implementation model to the output of the corresponding behavioral model to verify that the two algorithms are functionally equivalent.
Once the implementation algorithm is functionally verified to be equivalent to golden reference, HDL Coder can be used for Simulink to HDL code generation and HDL Verifier™ to Generate a Cosimulation Model (HDL Coder) test bench.
The second part of this two-part series shows how to generate HDL code from the implementation model and verify that the generated HDL code produces the same results as the floating-point behavioral model as well as the fixed-point implementation model.