Model Clock Recovery Loops in SerDes Toolbox
This example shows how to create detailed models of different types of serial channel clock recovery loops such as Alexander (bang-bang), Meuller-Muller, and Hogg & Chu.
Clocked Sampler Block
To model a clock recovery loop accurately, the representation of the clock edge times and the associated sampling of the data signal must be as precise as possible. This example demonstrates a method for accomplishing that within a model that uses a fixed step discrete sample time. This method is packaged inside a Clocked Sampler block that models both the clock oscillator and the data sampling latch.
The behavior of the clock oscillator and data sampling latch are very similar for different types of clock recovery loops. But the behavior and implementation of the phase detector and loop filter can vary much more widely. For example, for an Alexander clock recovery loop, the phase detection is boased on comparison of logic values latched at the rising and falling edges of the clock. In contrast, Hogg & Chu phase detection compares the timing of the clock falling edge with the data threshold crossing time, and Meuller-Muller phase detection depends solely on voltage sampling at the baud rate. The structure of the clock recovery loop model makes is as easy as possible to accommodate these differences.
Open the model SerDesClockRecovery attached to this example.
To generate a data signal for clock recovery, this model uses a data generator driving a lossy analog channel. Additional delay is inserted to introduce a delay offset with respect to the stimulus. The delayed data signal drives a single Clocked Sampler block that supplies a clock and data data samples to three different loop filters: an Alexander loop filter, a Meuller-Miller loop filter, and a Hogg & Chu loop filter. You can slect the output of any one of these three loop filters as the feedback signal to control the Clocked Sampler using the switches provided. Insert a one sample delay to avoid an algebraic loop.
Use scope displays to view the data signal and the clock recovery feedback signal.
The Clocked Sampler, Alexander Loop Filter, Meuller-Muller Loop Filter, and Hogg & Chu Loop Filter are all implemented as system objects. The example contains the source code for these system object classes. This code structure was chosen to present the algorithmic relationship between the Clocked Sampler and the loop filter as clearly as possible. To implement this functionality within a SerDes Toolbox receiver you must combine the algorithmic content into a single object class that more closely resembles the serdes.cdr object class.
Within the Clocked Sampler, the rising and falling clock edge times are represented as floating point numbers that are calculated to include the effects of phase noise and clock offset frequency as well as the period offset control signal. When a clock edge time is greater than the previous sample time but less than the current sample time, the data signal at the clock edge time is sampled using linear interpolation between the current and previous data signal values. The rising edge sample value, falling edge sample value, clock signal value and recorded clock time are all updated at the sample time following each clock edge. The timing in the loop filter is not critical, and loop filter processing can be performed at the sample time when the loop filter receives a clock transition.
Alexander (Bang-Bang) Clock Recovery
The Alexander clock recovery loop detects the clock phase by determining whether the sign of the data signal at the falling edge of the clock matches the sign of the data signal at the rising edge of the clock that occurred either before or after the falling edge. If the sign at the falling edge matches the sign at the previous rising edge but not the subsequent rising edge, then the clock is early. Conversely, if the sign at the falling edge matches the sign at the subsequent rising edge but not the sign at the previous rising edge, then the clock is late. The loop filter is an up-down counter that produces either a positive (early) or negative (late) pulse when it overflows. For a detailed explanation of an Alexander clock recovery loop, see Clock and Data Recovery in SerDes System.
The initial configuration of the SerDesClockRecovery model selects the output of the Alexander loop filter to control the clock phase in the Clocked Sampler.
Run the simulation and plot the time history and the histogram of the recovered clock phase. Save the time history of the recovered clock phase to the base workspace so that you can analyze it as you choose.
simout = sim(gcs); ctBB = plotClockTimes(simout);
Meuller-Muller Clock Recovery
The Meuller-Muller clock recovery algorithm assumes that the data waveform changes fastest when there is a transition between data symbol values, such as a transition from a one to a zero for an NRZ data signal. This assumption enables the clock recovery loop to use one quantitative voltage per symbol, wich is an advantage at high data rates. The time error estimate for the example's Meuller-Muller Loop Filter is drawn from CLOCK AND DATA RECOVERY FOR HIGH-SPEED ADC-BASED RECEIVERS, section 2.3.1
where is the previous voltage sample, is the current voltage sample, is the previous latched symbol value and is the current latched symbol value.
To evaluate the response of the Meuller-Muller clock recovery loop, move the Filter Select 1 switch to its second input port. Run the simulation and add the time history of the recovered clock phase and clock phase histogram to the figures that have already been created for the Alexander clock recovery loop. Save the time history of the clock phase to the base workspace so that you can analyze it later.
set_param([gcs '/Filter Select 1'],'sw','0'); simout = sim(gcs); ctMM = plotClockTimes(simout);
Hogg & Chu Clock Recovery
The Hogg & Chu clock recovery algorithm performs a relatively direct measurement of the clock phase by measuring the time between the threshold crossing of the data signal and the falling edge of the recovered clock. While blocks could be added to the example model to measure the data signal threshold crossing time directly, the Hogg & Chu Loop Filter in this example uses the simplifying approximation that the data signal slope in the threshold crossing region is constant. As estimated once a threshold crossing has been confirmed by the the sample at the next clock edge, the time error is
where is the previously detected data symbol value, is the voltage recorded on the previous clock edge, and is the maximum data signal amplitude.
To evaluate the reponse of the Hogg & Chu clock recovery loop, move the Fiter Select 2 switch to its second input port. Run the simulation, and add the time history of the recovered clock phase and clock phase histogram to the figures that have already been created for the Alexander and Meuller-Muller clock recovery loops. Save the time history of the clock phase to the base workspace so that you can analyze it later.
set_param([gcs '/Filter Select 2'],'sw','0'); simout = sim(gcs); ctHC = plotClockTimes(simout);