High-speed electronic systems suffer from signal degradation caused by various impairments such as impedance mismatch, attenuation, and crosstalk. Using the equalization and gain modulation blocks in the SerDes Toolbox™, you can compensate for the distortions introduced by the lossy channels.
Starting with the SerDes Designer app, you can design the top-level SerDes systems and perform statistical analysis. Use the building blocks and system objects to design, configure, simulate and analyze the SerDes system including the transmitter and the receiver.
|SerDes Designer||Design and analyze SerDes systems for export to Simulink, MATLAB and IBIS-AMI|
|DFECDR||Decision feedback equalizer (DFE) with clock and data recovery (CDR)|
|CDR||Models a clock data recovery circuit|
|FFE||Models a feed-forward equalizer|
|CTLE||Models continuous time linear equalizer (CTLE)|
|AGC||Automatically adjusts gain to maintain output waveform amplitude|
|VGA||Models a variable gain amplifier|
|SaturatingAmplifier||Models a saturation amplifier|
|PassThrough||Propagates baseband signal without modification|
|Analog Channel||Construct loss model from channel loss metric or impulse response|
|Configuration||Configure system wide settings in SerDes system model|
|Eye Diagram Scope||Display eye diagram of time-domain signal|
|Stimulus||Set pseudorandom binary sequence (PRBS) pattern and number of symbols to simulate in SerDes model|
|Decision feedback equalizer (DFE) with clock and data recovery (CDR)|
|Performs clock data recovery function|
|Models a feed-forward equalizer|
|Continuous time linear equalizer (CTLE) or peaking filter|
|Automatically adjusts gain to maintain output waveform amplitude|
|Models a variable gain amplifier|
|Models a saturating amplifier|
|Propagates baseband signal without modification|
This example shows how to use the SerDes Designer app to create and analyze a SerDes system, and create the IBIS-AMI models for the transmitter and receiver from Simulink®.
Basic components that build up a SerDes system.
Explore the behavior, control and characteristics of a first order clock data recovery (CDR).