Détecter et débugger les erreurs logiques
Identifiez les erreurs logiques dans lesquelles les conditions de couverture ne peuvent pas satisfaire toutes les valeurs attendues en utilisant la détection de logique morte.
Rubriques
- Dead Logic Detection
Describes the two analysis modes for dead logic detection in Simulink® Design Verifier™.
- Common Causes for Dead Logic
Describes several scenarios that results in dead logic.
- Detect Dead Logic Caused by an Incorrect Value
Example showing how to find an incorrect input specification using a dead logic result.
- Check for Specified Minimum and Maximum Value Violations
Describes how to analyze the model to verify that specified design minimum and maximum values are honored.
- Analyze Models for Design Errors
Run a Design Error Detection Analysis and interpret the results.
Sélection d՚exemples
Analyze Results for Dead Logic Analysis
Demonstrates how to isolate potential causes of dead logic using the sldvexCommonCausesOfDeadLogic model. Dead logic detection finds unreachable objectives in the model that cause the model element to remain inactive.
Debug Enhanced Modified Condition Decision Coverage Using Model Slicer
Find the Simulink Design Verifier generated objectives related to a specific model object using Model Slicer.
