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Zynq and FMCOMMS2/3/4 Receiver Configuration

Connect hardware logic to FMCOMMS Zynq radio receiver hardware

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Use of this block is not recommended. Use AD936x Data Read instead. For more information, see Version History.

Add-On Required: This feature requires the SoC Blockset Support Package for AMD FPGA and SoC Devices add-on.

  • Zynq and FMCOMMS2/3/4 Receiver Configuration block

Libraries:
SoC Blockset Support Package for Xilinx Devices / MPSoC / ZCU102
SoC Blockset Support Package for Xilinx Devices / Zynq-7000 / ZC706
SoC Blockset Support Package for Xilinx Devices / Zynq-7000 / ZedBoard

Description

The Zynq and FMCOMMS2/3/4 Receiver Configuration block connects to the FMCOMMS2/3/4 radio receiver hardware in your hardware logic. In simulation, this block provides optional ports for center frequency and gain, which the SoC Builder tool maps to hardware pins. The block does not connect to the radio hardware from simulation.

Examples

Packet-Based ADS-B Transceiver

Packet-Based ADS-B Transceiver

Packet-based systems are common in wireless communications. Data is received over the air and is decoded as discrete packet data on a compute device. For given system requirements, it is difficult to design a system and implement directly on SoC as it often involves long iterations of debugging and integration on hardware since hardware effects are difficult to account for at design time. In this example, you will design packet-based airplane tracking application based on Automatic Dependent Surveillance Broadcast (ADS-B) standard, partitioned between FPGA and embedded processor. Unlike traditional methods, you will simulate the application design with memory interface before implementation on hardware using SoC Blockset™ to shorten development time. You will then validate the design on hardware by automatically generated code from the model.

Transmit and Receive Tones Using AD9361 Dual-Channels

Transmit and Receive Tones Using AD9361 Dual-Channels

Design, simulate, and deploy dual-channel application system with AD9361 RF card using SoC Blockset™ on Xilinx® Zynq® UltraScale+™ MPSoC ZCU102 Evaluation Kit.

Limitations

  • In the hardware setup, select one of the supported Xilinx Zynq boards. You can find the supported boards in the Libraries list at the top of this page. Set Add-on Card to None.

  • This block supports SoC generation using the SoC Builder tool. This block does not support the IP core generation workflow. For more information on workflows, see SoC Generation Workflows.

Ports

Input

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External RF center frequency, specified as a nonnegative finite scalar on the port. The valid center frequency range is from 70 MHz to 6 GHz.

Dependencies

To enable this port, set the Source of center frequency parameter to Input Port.

Data Types: double

External gain, specified as a numeric scalar or a 1-by-2 numeric vector. The valid gain range is –10 dB to 77 dB. The resolution is 0.25 dB.

Set the gain based on the Channel mapping parameter configuration.

  • For a single channel, specify the gain as a scalar.

  • For two channels that use the same gain value, specify the gain as a scalar. The block applies the gain by scalar expansion.

  • For two channels that use different gain values, specify the gain as a 1-by-2 vector. The ith element of the vector is applied to the ith channel specified by the Channel mapping parameter.

Dependencies

To enable this port, set the Source of gain parameter to Input Port.

Data Types: double

Parameters

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The Zynq and FMCOMMS2/3/4 Receiver Configuration block supports up to two channels to receive data. Use the Channel mapping parameter to indicate whether to use a single channel or dual channels. For each channel, you can set the Gain (dB) parameter independently, or you can apply the same setting to all channels. All other parameter values are applied to each channel in use.

Main

Source of center frequency, specified as one of these options:

  • Dialog — Set the center frequency by using the Center frequency (Hz) parameter.

  • Input Port — Set the center frequency by using the center frequency input port.

RF center frequency, in Hz, specified as a nonnegative scalar. The valid range for center frequency is 70 MHz to 6 GHz.

Dependencies

To enable this parameter, set Source of center frequency to Dialog.

Data Types: double

Source of gain, specified as one of these options:

  • AGC Slow Attack –– Use this mode for signals with a slowly changing power level.

  • AGC Fast Attack –– Use this mode for signals with a rapidly changing power level.

  • Dialog — Specify the gain by using the Gain (dB) parameter.

  • Input Port — Specify the gain by using the gain input port.

Gain, in dB, specified as a numeric scalar or a 1-by-2 numeric vector. The valid gain range is –10 dB to 77 dB. The resolution is 0.25 dB.

Set the gain based on the Channel mapping parameter configuration.

  • For a single channel, specify the gain as a scalar.

  • For two channels that use the same gain value, specify the gain as a scalar. The block applies the gain by scalar expansion.

  • For two channels that use different gain values, specify the gain as a 1-by-2 vector. The ith element of the vector is applied to the ith channel specified by the Channel mapping parameter.

Dependencies

To enable this parameter, set Source of gain to Dialog.

Data Types: double

Channel output mapping, specified as one of these values:

  • 1 — Specify this option to use channel 1.

  • 2 — Specify this option to use channel 2.

  • [1 2] — Specify this option to use both the channels.

Baseband sampling rate, in Hz, specified as a positive scalar. The valid range of this parameter is 520.834 kHz to 61.44 MHz.

Data Types: double

Advanced

When you select this parameter, the block applies in-phase and quadrature (IQ) imbalance compensation.

When you select this parameter, the block applies an RF direct current (DC) blocking filter.

When you select this parameter, the block applies a baseband DC blocking filter.

Extended Capabilities

Version History

Introduced in R2019a

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See Also