Display messages, events, states, transitions, and functions between blocks during simulation
Simulink / Messages & Events
The Sequence Viewer block displays messages, events, states, transitions, and functions between certain blocks during simulation. The blocks that you can display are called lifeline blocks and include:
Blocks that contain messages, such as Stateflow® charts
Blocks that call functions or generate events, such as Function Caller, Function-Call Generator, and MATLAB Function blocks
Blocks that contain functions, such as Function-Call Subsystem and Simulink Function blocks
To see states, transitions, and events for lifeline blocks in a referenced model, you must have a Sequence Viewer block in the referenced model. Without a Sequence Viewer block in the referenced model, you can see only messages and functions for lifeline blocks in the referenced model.
The Sequence Viewer block does not display function calls generated by MATLAB Function blocks and S-functions.
Time Precision for Variable Step — Digits for time increment precision
3 (default) | scalar
Number of digits for time increment precision. When using a variable step
solver, change this parameter to adjust the time precision for the sequence
viewer. By default the block supports
3 digits of
Suppose the block displays two events that occur at times
these two events precisely requires
4 digits of
precision. If the precision is
3, then the block displays
two events at time
|Type: character vector|
History — Maximum number of previous events to display
5000 (default) | scalar
Total number of events before the last event to display.
For example, if History is
10 events in your simulation, then the block
6 events, including the last event and the five
events prior the last event. Earlier events are not displayed. The time
ruler is greyed to indicate the time between the beginning of the simulation
and the time of the first displayed event.
Each send, receive, drop, or function call event is counted as one event, even if they occur at the same simulation time.
|Type: character vector|
C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.
This block can be used for visualizing message transitions during simulation, but is not included in the generated code.
HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.
This block displays messages during simulation when used in subsystems that generate HDL code, but it is not included in the hardware implementation.