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System object: hdlverifier.FPGADataReader
Package: hdlverifier

Display data types for all captured signals




displayDataTypes(DC) displays the data type configured for each data capture signal. The default data type depends on the bit width of the captured signal. This size is the width you specified for the port on the generated IP. If the signal is 8, 16, or 32 bits, the default is uint. If the signal has one bit, the default is boolean. If the signal is a different width, the default is numerictype(0,bitWidth,0). Use the setDataType method to modify the data type of a signal.

Input Arguments

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This object is the customized object you created using the FPGA Data Capture Component Generator app.