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configureDACTile

Configure the PLL and sampling rate of DAC tile

Description

configureDACTile(rfDataConverter,tileId,PLLSrc,PLLRefClk,samplingRate) configures the source and reference clock of the phase-locked loop (PLL) and sampling rate of the specified DAC tile.

Input Arguments

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RF data converter, specified as an soc.RFDataConverter object. Via Ethernet, this object connects the host computer to the RF data converter on the connected SoC device. Use the object functions and properties of this object to configure the RF data converter.

ID of the RF-DAC tile connected to the programmable logic, specified as 0, 1, 2, or 3. Available options for the RF-DAC tile ID vary as per the specified RFSoC device. A tile contains several DACs, accessible as channels, and several shared timing units, including a clock and PLL.

Data Types: double

Source clock signal of the PLL in the RF-DAC tile, specified as "Internal" or "External LMK/LMX". The source clock signal can come from either the clock in the tile or the external source.

Data Types: char | string

Frequency of the reference clock to the PLL, specified as a positive scalar. This reference clock frequency drives the PLL in the RF-DAC tile.

Data Types: double

Sampling rate in MHz, specified as a positive scalar.

Data Types: double

Version History

Introduced in R2020b