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Frequency Hopping Using Xilinx RFSoC Device

This example shows how to design and implement frequency hopping algorithm using Xilinx® RF Data Converter numerically controlled oscillator (NCO) real-time ports. Frequency hopping is widely used in Bluetooth, code division multiple access (CDMA) and frequency hopping spread spectrum (FHSS) applications. FHSS is a technique employed to reduce interference and eavesdropping. To design the algorithm and implement on Xilinx® Zynq® UltraScale+™ RFSoC ZCU111 evaluation kit, use Simulink® and SoC Blockset®.

Supported Hardware Platforms

  • Xilinx Zynq UltraScale+ RFSoC ZCU111 evaluation kit and XM500 balun card

Design Task and System Specifications

In this example, the design task is to design a frequency hopping algorithm with RF Data Converter NCO real time ports. To design frequency hopping in transmit path of RFDC, generate a tone using NCO HDL optimized block and sends the NCO control signals to the DAC NCO real time ports. Similarly, in the receive path sends the NCO control signals to ADC NCO real time ports for frequency hopping. To verify the frequency hopping in transmit path, loopback the DAC and ADC channel and receive the data back on the FPGA from the ADC with the following system specifications.

System Specifications

  • ADC and DAC sampling rate = 2048 MSPS

  • Number of ADC channels = 1

  • Number of DAC channels = 1

  • Digital data interface = IQ

  • Frequency hopping step size = 25 MHz

  • Frequency hopping sweep rate = 32 micro seconds (us)

Design Using SoC Blockset

Create an SoC model soc_frequency_hopping_top as the top model and set the hardware board to Xilinx Zynq Ultrascale+ RFSoC ZCU111 evaluation kit. This model includes the FPGA model soc_frequency_hopping_fpga and the processor model soc_frequency_hopping_proc, which are instantiated as model references. The top model also includes the AXI4-Stream to Software block, which model the DDR memory interface for the data transfers between FPGA and processor.

open_system('soc_frequency_hopping_top')

close_system('soc_frequency_hopping_top')

RF Data Converter Configuration

An RFSoC device has its RF data converter connected to the programmable logic. To configure the ADC and DAC settings, use the RF Data Converter block. The block provides an interface to the Xilinx RF Data Converter IP in Simulink for modeling a wireless system destined for implementation on a Xilinx RFSoC device.

To meet the system specifications, you must choose the Interpolation mode, Decimation mode, and Samples per clock cycle parameters such that the effective clock cycle (sample rate) for the wireless algorithm FPGA is in the desirable range. After you click Apply, the parameter values are displayed on the block under Stream clock frequency parameter.

For this example, in the DAC tab, set the Interpolation mode parameter to 4 and the Samples per clock cycle parameter to 2. In the ADC tab, set the Decimation mode parameter to 4 and the Samples per clock cycle parameter to 2. These values imply a Stream clock frequency value of 2048/(4*2) = 256 MHz. In the Advanced tab select the NCO Real Time Ports parameter under the DAC and ADC tabs.

Hardware Logic Design

open_system('soc_frequency_hopping_fpga')

close_system('soc_frequency_hopping_fpga')

The FPGA model soc_frequency_hopping_fpga contains Frequency Hopping subsystem, which is connected to the DAC and ADC portion of the RF data converter block, and the RFDC NCO real time ports. The Frequency Hopping contains three subsystems, FH Transmitter, FH Receiver, and FH Controller. The FH Transmitter subsystem models the logic for generating the sinusoid tone signal under the subsystem Tone Generation. The logic uses a NCO block to generate 1 MHz tone. The NCO updater subsystem models the logic to generate control signals NCO Frequency, NCO Phase, NCO reset, and NCO UpdateEvent. These signals are connected to the real-time ports of the RF Data Converter block.

The FH Receiver subsystem has Down sampler and Update NCO Frequency which sends NCO control signals to ADC real time ports. The received signal from ADC downsampled and sends to processor for display.

The FH Controller subsystem controls the FH Transmitter and FH Receiver subsystems. It sends different controls such as DAC and ADC mixer frequencies and trigger events to control the hop rate.

Processor Logic Design

The processor receives the data from the FPGA and sends it to the host computer where it can be visualized using Spectrum Analyzer. The processor also models some control signals for the FPGA algorithm to initialize the system. The processor logic contains an event-based task driven by the arrival of data from the FPGA. The processor algorithm task is denoted as dataTask in the Task Manager block and is specified as event driven. The Task Manager block schedules data asynchronously by means of the buffer ready event rdEvent in the memory, denoting the arrival of a frame of data from the FPGA. The algorithm itself is modeled under the Processor Algorithm Wrapper subsystem in the processor model soc_frequency_hopping_proc and connected to the Task Manager block at the top level. To operate on the data received as a frame of four packed samples with the uint64 data type, you must first unpack and restore the signedness of the data. Connect the Processor Algorithm Wrapper subsystem to the Spectrum scope for visualization. In a separate Initialize Function subsystem, initialize the various registers on the FPGA subsystems with their default values.

open_system('soc_frequency_hopping_proc')

close_system('soc_frequency_hopping_proc')

Simulate

Run the model and visualize the frequency hopped signal generated from the FPGA on the DAC Mixer Output spectrum analyzer scope. You can observe the frequency hopping signal with 25 MHz step size.

The transmitted signal is looped back to the ADC ports of the RFDC block and captured using the FH Receiver subsystem in the FPGA model. In the processor system, visualize the waveform in the frequency domain using the ADC Captured Signal spectrum scope. Observe the data on the spectrum scope with a substantial delay after the start of the simulation. This delay is because of the delay in the availability of the first frame of data through the DDR4 to the scope, which is due to the length of the loopback data path.

Observe the received signal that shows a constant tone of 1 MHz as same frequency hopping in both transmit and receive paths.

Implement and Run on Hardware

Hardware Setup

Connect the SMA connector on the XM500 balun card to complete the loopback between the DAC and ADC, according to these connections.

DAC229_T1_CH2(J5) to ADC224_T0_CH0(J4).

To implement the model on a supported SoC board, use the SoC Builder tool. The SoCBuilder tool is a step by step tool to generate the bitstream and software application from the Simulink model for the specified hardware board. Ensure that the Hardware Board is set to Xilinx Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit in the System on Chip tab of the Simulink toolstrip. Before running the SoCBuilder modify the downSamplingFactor to 128 from the command line.

To open SoC Builder, click Configure, Build, & Deploy. After the SoC Builder tool opens, follow these steps.

  1. Select Build Model on the Setup screen. Click Next.

  2. Click Next on the Review Task Map screen.

  3. Click View/Edit Memory Map on the Review Memory Map screen to view the memory map. Click Next.

  4. Specify the project folder on the Select Project Folder screen. Click Next.

  5. Select Build External mode on the Select Build Action screen. Click Next.

  6. Click Validate on the Validate Model screen to check the compatibility of the model for implementation. Click Next.

  7. Click Build on the Build Model screen to begin building the model. An external shell opens when FPGA synthesis begins. Click Next.

  8. Click Test Connection on Connect Hardware screen to test the connectivity of the host computer with the SoC board. Click Next to go to the Run Application screen.

The FPGA synthesis takes more than 30 minutes to complete. To save time, you can use the provided pregenerated bitstream by following these steps.

  1. Close the external shell to terminate the FPGA synthesis.

  2. Copy the pregenerated bitstream to your project folder by entering this command at the MATLAB command prompt.

copyfile(fullfile(matlabshared.supportpkg.getSupportPackageRoot,'toolbox','soc','supportpackages','xilinxsoc','xilinxsocexamples','bitstreams','soc_frequency_hopping_top-XilinxZynqUltraScale_RFSoCZCU111EvaluationKit.bit'),'./soc_prj');

Click Load and Run button to load the pregenerated bitstream and run the model on the SoC board.

After the bit file is loaded, open the generated software model.

Run the model in external mode by clicking Monitor & Tune. You can control the configuration from the Simulink model. Before running the model in external mode modify the downSamplingFactor to 128 and freqSweepRate to 1 second from the command line. Copy the spectrum analyzer from the top model and connect to the rate transition block as shown in this figure, and run the model. You can observe the received signal waveform of 1 MHz in the spectrum analyzer as frequency hopping in both transmit and receive paths with same frequency step and sweep rate. To see the frequency shift in received signal waveform, set dacFrequencyRange to [500e6 501e6 0.5e6] and adcFrequencyRange to [-500e6 -500e6 0].

Summary

The example demonstrated how to model FPGA and processor algorithms to perform frequency hopping on RFSoC device. You modeled FPGA logic to transmit a signal and employed the real-time ports of the RF Data Converter for frequency hopping. You verified the system by looping back the transmitted signals into the FPGA using ADC ports and visualizing the spectrum. You can extend this model to develop your own frequency hopping algorithm in Simulink and implement on the RFSoC device.