Problems with the HDL Workflow Advisor

Hi,

i am trying to convert a MATLAB function into VHDL code with the HDL workflow advisor and i want to verify it with the FPGA-in-the-loop. With a simple function and testbench (see attachement function1 below) it works but with little changes (see attachement function2 below) my computer hangs or crashes during "Verify with FPGA-in-the-loop" at the point "Running programmable file generation..." and there are no error messages.

I think both should work because the functions are very simple. Anybody an idea?

best regards Niko

Answer 1

[Varun Bhaskar]

Hi,

Please reach out to Technical Support and they should be able to assist you by creating a case. Kindly provide them with the project file too.