Modeling and Simulation of High-Speed Links & Interconnects
Overview
This webinar aims to streamline the system design and analysis process, enabling participants to efficiently transition from initial SerDes system floor planning to detailed system design and robust signal integrity analysis. By focusing on practical, tool-driven methodologies, the webinar seeks to empower engineers to overcome common pitfalls in system design, ensuring high-performance, reliable communication systems in an era of ever-increasing data rate requirements.
Highlights
- SerDes floor planning with SerDes Designer App
- Detailed SerDes design and IBIS-AMI generation with Simulink
- Comprehensive signal integrity simulation and analysis
- Presentation from Ranjan Sahoo of NXP on how NXP Semiconductors Streamlines High-Speed Interface Design with SERDES Toolbox
About the Presenter
Ranjan Sahoo | Technical Director, SCE | NXP Semiconductors
Ranjan K Sahoo is a seasoned technology leader with over 22 years of experience in the semiconductor industry, having worked with renowned organizations such as Cypress, Intel, and NXP. He currently serves as a Technical Director, SCE, focusing on high-speed interfaces including USB 3.2 and DisplayPort 1.4.
He holds an M.Tech degree in VLSI Design from IIT Madras and brings deep technical expertise in high-speed circuit and system design, analog circuit design, and digitally assisted system performance optimization
Jahnavi Dhulipala | Senior Application Engineer| MathWorks
Jahnavi Dhulipala is a senior application engineer at MathWorks and is based in Bangalore. She specializes in RF, analog, and mixed-signal component and system design and works with tier-1 semiconductor and electronics companies to help support their adoption and success with top-down and model-driven system design and verification workflows.
Product Focus
This event is part of a series of related topics. View the full list of events in this series.
