Faraday Accelerates SIP Development and Shrinks NAND Flash Controller ECC Engine Gate Count by 57% with Model-Based Design

In Faraday’s development workflow, engineers create design modules that they can rapidly configure and assemble into integrated system-level models. In the past, these modules were hand coded in SystemC, C++, or Verilog ^®. When memory controller standards changed, the modules had to be recoded. Not only did hand coding take time, but the modules often had to be ported into another language for RTL simulation on proprietary simulation platforms.

When Faraday’s modules included discrete-time interactions, the simulations them­selves were slow. For example, modules that control the flow of data for double data rate (DDR) memory or flash memory must employ a sophisticated communications protocol and manage large amounts of data. Simulating these modules proved so slow that to meet their deadline, Faraday had to limit design iterations and tests. With little time for optimization, the engineers designed for the worst-case scenario, which led to suboptimal designs with more gates—and a higher cost—than necessary.

Faraday engineers established a new workflow in which they use MATLAB^®, Simulink^®, and Stateflow^® to model and simulate their system-level designs and Simulink Coder™ and HDL Coder™ to generate code from their models.

Working in Simulink and Stateflow, the engineers modeled multiple design modules, including finite state machines (FSMs) for the DDR and flash controllers. They performed extensive simulations in Simulink to ensure that the models were cycle accurate for a range of configurations. They used MATLAB to run statistical analysis on the models.

In the architecture design phase, Faraday engineers evaluated various combinations of modules and tried different parameter values. They used their simulation results to optimize and improve the designs. “Stateflow makes it easy for engineers to communicate complex controller designs in detail and at a level of abstraction that is easy to understand,” says Chen.

As a faster alternative to RTL simulation, Faraday engineers used Simulink Coder to generate C code from their model. This C code provides a programmer’s view of the design and can be integrated into many virtual platform solutions for software development and system-level architecture exploration.

In the implementation phase, instead of manually coding their design, Faraday engineers used HDL Coder to automatically generate HDL code from the same Simulink model for integration into their RTL simulation. This workflow has enabled Faraday to shorten their design process as they moved from architecture design to an FPGA-based prototype.

Faraday has completed the DDR and flash controller projects and delivered the SIP designs to their customer on schedule. The engineering team is positioned to accelerate development on future memory controller projects by reusing and adapting their existing models.