High-Throughput HDL Algorithms

DSP HDL Toolbox™ provides blocks to implement high-bandwidth applications such as radar, SIGINT, and 5G FR2 wireless. To meet their bandwidth requirements, these applications need to process incoming data as multiple samples in parallel, or frame-based processing. Frame-based processing increases throughput by implementing the algorithm in parallel on each sample in the input vector. These implementations increase data throughput but use more hardware resources. The ports of blocks that support frame-based processing accept column vector input and output signals. Each element of the vector represents a sample in time. Using frame-based input can achieve gigasamples-per-second (GSPS) throughputs. These high-throughput rates are also referred to as super-sample rates.

Blocks that Support Frame-Based Input

Supported Block	Parameters to Enable Frame Input	Limitations
FFT and IFFT	Connect a column vector to the input data port. The vector size must be a power of 2 between 1 and 64 and cannot be greater than the FFT length.	Frame-based input is supported only when Architecture is set to Streaming Radix 2^2.
Channelizer and Channel Synthesizer	Connect a column vector to the input data port. The vector size must be a power of 2 between 1 and 64 and cannot be greater than the FFT length.
Discrete FIR Filter	Connect a column vector to the input data port. The vector size must be a power of 2 between 1 and 64.	You cannot use frame-based input with the partly-serial architecture.
Biquad Filter	Connect a column vector to the input data port. The input vector size can be up to 64 samples, but large vector sizes can make the calculation of internal datatypes challenging. Vector sizes of up to 16 samples are practical for hardware implementation.	Vector input is supported only when you set Filter structure to Pipelined feedback form.
FIR Decimator	Connect a column vector to the input data port. The vector size must be less than or equal to 64 samples.	You cannot use frame-based input with Minimum number of cycles between valid input samples greater than 1. When the vector size is less than the decimation factor, the decimation factor must be an integer multiple of the vector size. When the vector size is greater than the decimation factor, the vector size must be an integer multiple of the decimation factor.
FIR Interpolator	Connect a column vector to the input data port. The vector size must be less than or equal to 64 samples.	You cannot use frame-based input with Minimum number of cycles between valid input samples greater than 1.
CIC Decimator	Connect a column vector to the input data port. The input vector size can be up to 64 samples.	Vector input is not supported with programmable decimation rate.
CIC Interpolator	Connect a column vector to the input data port. The input vector size can be up to 64 samples.	Vector input is not supported with programmable interpolation rate.
NCO	Set the Samples per frame parameter to the desired output vector size.
Complex to Magnitude-Angle	Connect a column vector to the input data port. The input vector size can be up to 64 samples.
Delay	Connect a column vector to the input port. The input vector size can be up to 512 samples. Set the Input processing parameter to Columns as channels (frame-based).

Related Topics

• High-Throughput Channelizer for FPGA