The output, y, is a vector of the same length as the input vectors, and with a word length equal to the sum of the word lengths of the two input vectors.
Perform Element-by-Element Concatenation of Two Matrices
When the inputs are both matrices of the same size, bitconcat performs element-wise concatenation of the two matrices and returns a matrix of the same size.
Create two fixed-point matrices.
a = fi([1,2,5;7,4,5;3,1,12],0,4,0);
disp(bin(a))
0001 0010 0101
0111 0100 0101
0011 0001 1100
b = fi([6,1,7;7,8,1;9,7,8],0,4,0);
disp(bin(b))
0110 0001 0111
0111 1000 0001
1001 0111 1000
Perform element-by-element concatenation of the bits of a and b.
Input array, specified as a scalar, vector, matrix, or multidimensional
array of fixed-point fi objects. bitconcat accepts varargin number
of inputs for concatenation.
Input array, specified as a scalar, vector, matrix, or multidimensional
array of fixed-point fi objects. If b is
nonscalar, it must have the same dimension as the other inputs.
Output array, specified as a scalar, vector, matrix, or multidimensional
array of unsigned fixed-point fi objects.
The output array has word length equal to the sum of the word
lengths of the inputs and a fraction length of zero. The bit representation
of the stored integer is in two's complement representation. Scaling
does not affect the result type and value.
If the inputs are all scalar, then bitconcat concatenates
the bits of the inputs and returns a scalar.
If the inputs are all arrays of the same size, then bitconcat performs
element-wise concatenation of the bits and returns an array of the
same size.
Extended Capabilities
C/C++ Code Generation Generate C and C++ code using MATLAB® Coder™.
HDL Code Generation Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.
For VHDL®, generates the concatenation operator: (a &
b).
For Verilog®, generates the concatenation operator: {a ,
b}.
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