When you generate HDL code, you can optionally generate an HDL test bench that verifies the generated HDL DUT against test vectors saved from your Simulink model.
|Generate HDL test bench from model or subsystem|
Learn how HDL test bench generation works.
Select a generated test bench.
Generate a HDL test bench from Configuration Parameters dialog box for FIR filter model.
Learn how to generate a HDL test bench to verify the VHDL or Verilog Code.