Native Floating Point
You can generate HDL code from your floating-point designs by using HDL Coder™ native floating-point support. When you work with floating-point designs, HDL Coder supports:
Target-independent HDL code generation that you can deploy on an FPGA or ASIC device.
The full range of IEEE-754 features including denormal numbers, exceptions, and rounding modes.
Math and trigonometric functions.
Floating-point designs have better precision, higher dynamic range, and a shorter development cycle than fixed-point designs. If your design has complex math and trigonometric operations, use native floating-point technology.
|Floating-point target configuration for floating-point library|
|IP settings for selected floating-point configuration|
|Create floating-point target configuration for floating-point library that you specify|
- Getting Started with HDL Coder Native Floating-Point Support
Learn about the native floating point support in HDL Coder.
- Generate Target-Independent HDL Code with Native Floating-Point
Generate HDL code from floating-point Simulink® models.
- Numeric Considerations for Native Floating-Point
Learn about nearest even-digit rounding, denormal numbers, exception handling, and relative accuracy and ULP considerations.