Compile command for Verilog^® or SystemVerilog

Format name used to write the Cmd section of the compilation script

Model Configuration Pane: EDA Tool Scripts

Description

Format name passed to fprintf to write the Cmd section of the compilation script for Verilog or SystemVerilog files.

Settings

vlog %s %s\n (default)

Default: vlog %s %s\n

The command-per-file phase (Cmd) of the script is called iteratively, once per generated HDL file. On each call, a different file name is passed in.

The two implicit arguments in the compile command are the contents of the SimulatorFlags property and the file name of the current entity or module. To omit the flags, set SimulatorFlags property to '' (the default).

Tips

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

Recommended Settings

No recommended settings.

Programmatic Use

Parameter: HDLCompileVerilogCmd

Type: character vector

Default: 'vlog %s %s\n'

Version History

Introduced in R2012a