HDL Combinatorial Logic

R2026b

Implement truth table

Since R2024b

• 

HDL Combinatorial Logic block

To add a block to a model, double-click the canvas and start typing the block name. Then, select the block from the list.

Libraries:
HDL Coder / RCP and HIL

Description

The HDL Combinatorial Logic block implements a standard truth table for modeling programmable logic arrays (PLAs), logic circuits, decision tables, and other Boolean expressions. You can use this block in conjunction with Memory blocks to implement finite-state machines or flip-flops.

Examples

Model Two-Input AND Logic

This example builds a two-input AND function by using the HDL Combinatorial Logic block, which returns 1 when both input elements are 1, and 0 otherwise.

To implement this function, specify the Input table parameter value as logical([0 0; 0 1; 1 0; 1 1]) and the Output table parameter value as logical([0; 0; 0; 1]) in the HDL Combinatorial Logic block of this model.

open_system("HDLCombinatorialLogicBlockExample");

The following table shows the permutations of inputs that generate each output. The input signal labeled Input vector corresponds to the Input Vector columns in the table. The input values determine the row of the Output column of the table that is passed as block output. For example, if Input vector is [1 0], the input references the third row and the output value is 0.

Ports

Input

u — Input signal

vector

Input signal, specified as a vector. The type of signals accepted by an HDL Combinatorial Logic block depends on whether you selected the Boolean logic signals option (see Implement logic signals as Boolean data (vs. double)). If this option is enabled, the block accepts real signals of type Boolean or double.

Data Types: double | Boolean

Output

v — Output signal

scalar | vector

Output signal, returned as a double scalar or vector if the truth table represented by Input table and Output table contains non-Boolean values of type double; or returned as Boolean scalar or vector otherwise. The type of the output is the same as that of the input except that the block outputs double if the input is Boolean and the truth table contains non-Boolean values.

Data Types: double | Boolean

Parameters

Input table — Matrix of input permutations

matrix

The Input table parameter can have Boolean values (0 or 1) of any data type, including fixed-point data types. If the table contains non-Boolean values, the data type of the table must be double.

The relationship between the number of inputs and the number of rows is:

number of rows = 2^{(number of inputs)}

Simulink^® returns a row of the output matrix specified by Output table by computing number based on the input vector elements. Simulink computes the index by building a binary number where input vector elements having zero values are 0 and elements having nonzero values are 1, then adding 1 to the result. For an input vector, u, of m elements:

row index = 1 + u(m)×2⁰+ u(m-1)×2¹+ ... + u(1)×2^m-1

Programmatic Use

Block Parameter: inputTable

Type: character vector

Values: matrix

Default: logical([0 1; 1 0; 1 1])

Output table — Matrix of outputs

matrix

The Output table parameter can have Boolean values (0 or 1) of any data type, including fixed-point data types. If the table contains non-Boolean values, the data type of the table must be double.

Programmatic Use

Block Parameter: outputTable

Type: character vector

Values: matrix

Default: logical([1 0; 1 0; 1 1])

Programmatic Use: Add Block

To add the block programmatically, use the add_block function with one of these library block paths as the source.

"hdlsllib/RCP and HIL/HDL Combinatorial Logic"

Example: add_block("hdlsllib/RCP and HIL/HDL Combinatorial Logic","myModel/myBlock",MakeNameUnique="on")

Extended Capabilities

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

For HDL code generation, the Input table and Output table parameters must be specified as Boolean values or logical 1 (true) or 0 (false).

Version History

Introduced in R2024b