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Map pipeline delays to RAM

Map pipeline registers in the generated HDL code to RAM

Model Configuration Pane: Optimization

Description

Map pipeline registers in the generated HDL code to RAM. Certain speed or area optimizations such as pipelining and resource sharing, or certain block implementations that you specify can insert pipeline registers in the generated HDL code. You can save area on the target device by mapping these pipeline registers to RAM.

Settings

Off (default) | On
On

Map pipeline registers in the generated HDL code to RAM. To map these registers to block RAMs, the RAM size must be greater than or equal to the RAM mapping threshold in bits. To calculate the total RAM size for delays, use this formula: 

RAMSize = Delay length * Word length * Vector length * Complexity
Complexity is 2 for a complex data type or 1 for a real datatype.

Off

Do not map pipeline registers in the generated HDL code to RAM.

Tips

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can enable the MapPipelineDelaysToRAM setting when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

  • Pass the property as an argument to the makehdl function.

    makehdl('sfir_fixed/symmetric_fir', ... 
        'MapPipelineDelaysToRAM','on')

  • When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.

    hdlset_param('sfir_fixed','MapPipelineDelaysToRAM','on')
makehdl('sfir_fixed/symmetric_fir')

Recommended Settings

No recommendations.

Programmatic Use

Parameter: MapPipelineDelaysToRAM
Type: character vector
Value: 'on' | 'off'
Default: 'off'

Version History

Introduced in R2016a

See Also

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