Reset type
Reset logic for registers in HDL code
Model Configuration Pane: HDL Code Generation / Global Settings
Description
The Reset type parameter specifies whether to use asynchronous or synchronous reset logic when generating HDL code for registers.
Settings
Asynchronous
(default) | Synchronous
Asynchronous
Uses asynchronous reset logic. The reset logic samples the reset independently of the clock signal.
For example, this process block, generated by a Unit Delay block, uses asynchronous resets. When the reset signal asserts, the process block performs a reset without checking for a clock event.
Unit_Delay1_process : PROCESS (clk, reset) BEGIN IF reset = '1' THEN Unit_Delay1_out1 <= (OTHERS => '0'); ELSIF clk'event AND clk = '1' THEN IF clk_enable = '1' THEN Unit_Delay1_out1 <= signed(x_in); END IF; END IF; END PROCESS Unit_Delay1_process;
Synchronous
Uses synchronous reset logic. The reset logic samples the reset with respect to the clock signal.
For example, this process block, generated by a Unit Delay block, checks for the rising edge before performing a reset:
Unit_Delay1_process : PROCESS (clk) BEGIN IF rising_edge(clk) THEN IF reset = '1' THEN Unit_Delay1_out1 <= (OTHERS => '0'); ELSIF clk_enable = '1' THEN Unit_Delay1_out1 <= signed(x_in); END IF; END IF; END PROCESS Unit_Delay1_process;
Tips
To set this property, use the functions hdlset_param
or makehdl
. To view the property value, use
the function hdlget_param
.
For example, to set this property for a subsystem named symmetric_fir
in a
model named sfir_fixed
, use one of these methods:
Pass the property as an argument to the
makehdl
function.makehdl("sfir_fixed/symmetric_fir", ... "ResetType","async")
Use
hdlset_param
to set the parameter on the model and then generate HDL code usingmakehdl
.hdlset_param("sfir_fixed","ResetType","async") makehdl("sfir_fixed/symmetric_fir")
Programmatic Use
Parameter: ResetType |
Type: character vector |
Value:
"async" | "sync"
|
Default:
"async" |
Version History
Introduced in R2012a