SystemVerilog DPI test bench

R2026b

Enable SystemVerilog DPI test bench generation

Model Configuration Pane: HDL Code Generation / Test Bench

Description

The SystemVerilog DPI test bench parameter enables or disables generation of SystemVerilog DPI test bench. Select your HDL simulator by using the Simulation tool configuration parameter. The Custom setting for Simulation tool is not supported for test bench generation.

When you set this property, the code generator generates a direct programming interface (DPI) component for your entire Simulink^® model, including your DUT and data sources. Your entire model must support C code generation with Simulink Coder™. The code generator generates a SystemVerilog test bench that compares the output of the DPI component with the output of the HDL implementation of your DUT. The code generator also builds shared libraries and generates a simulation script for the simulator you select.

Consider using this option if the default HDL test bench takes a long time to generate or simulate. Generation of a DPI test bench is sometimes faster than the default version because it does not run a full Simulink simulation to create the test bench data. Simulation of a DPI test bench with a large data set is faster than the default version because it does not store the input or expected data in a separate file.

To use this capability, you must have HDL Verifier™ and Simulink Coder. To run the SystemVerilog test bench with the generated VHDL^® code, you must have a mixed-language simulation license for your HDL simulator.

Dependencies

To enable this parameter:

• Select Generated model.

• Set Generate HDL for to the DUT.

• Set Simulation tool to any value except Custom.

Settings

off (default) | on

off

Disable generation of SystemVerilog DPI test bench.

on

Enable generation of SystemVerilog DPI test bench.

Tips

To set this property, use the functions hdlset_param or makehdltb. To view the property value, use the function hdlget_param.

For example, to set this property for a subsystem named symmetric_fir in a model named sfir_fixed, use one of these methods:

• Pass the property as an argument to the makehdltb function.

  makehdltb("sfir_fixed/symmetric_fir", ... 
              "GenerateSVDPITestBench","ModelSim")

• Use hdlset_param to set the parameter on the model and then generate HDL code using makehdltb.

  hdlset_param("sfir_fixed","GenerateSVDPITestBench","ModelSim")
  makehdltb("sfir_fixed/symmetric_fir")

Programmatic Use

Parameter: GenerateSVDPITestBench

Type: character vector

Value: "None" | "ModelSim" | "Incisive" | "VCS" | "Vivado Simulator"

Default: "ModelSim"

Limitations

Your DUT subsystem must meet the following conditions:

• Input and output data types of the DUT cannot be larger than 64 bits.

• Input and output ports of the DUT cannot use enumerated data types.

• Input and output ports cannot be single-precision or double-precision data types.

• The DUT cannot have multiple clocks. You must set the Clock inputs code generation option to Single.

• Use trigger signal as clock must not be selected.

• If the DUT uses vector ports, you must set the Scalarize ports parameter to on or DUT Level to flatten the interface. Configure this parameter programmatically by using hdlset_param or makehdl functions.

• If the DUT uses non-virtual ports and Target language is VHDL or SystemVerilog, you must set the Preserve Bus structure in the generated HDL code parameter to off. Configure this parameter programmatically by using hdlset_param or makehdl functions.

Version History

Introduced in R2017a