Run and Verify IP Core

Prototype, simulate, and verify the generated IP core on your target FPGA device

Run and verify the generated bitstream from your IP core design on your target hardware. The input is a generated bitstream for the FPGA portion of your device. The output is a simulated and verified design running on your target FPGA. For more details on the workflow, see Targeting FPGA & SoC Hardware Overview.

Run and Verify IP Core on Target Hardware Workflow

Objects

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Target Connection

`fpga`	Access target FPGA or SoC device from MATLAB
`hdlcoder.DUTPort`	DUT port from an HDL Coder generated IP core, saved as an object array
`xilinxsoc`	Connection to processor on Xilinx SoC board
`intelsoc`	Connection to processor on Intel SoC board

Functions

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Target Connection Interfaces

`addAXI4SlaveInterface`	Write data to IP core or read data from IP core using AXI4 or AXI4-Lite interface
`addAXI4StreamInterface`	Write data to IP core or read data from IP core using AXI4-Stream interface
`addMemoryInterface`	Access memory regions on your FPGA or SoC hardware
`mapPort`	Maps a DUT port to specified AXI4 interface in HDL IP core
`writePort`	Write data to a DUT port from MATLAB
`readPort`	Reads output data and returns it with the port data type and dimension
`writeMemory`	Write data to memory regions on FPGA or SoC hardware
`readMemory`	Read data from memory regions on FPGA or SoC hardware using MATLAB
`release`	Release the hardware resources associated with the fpga object
`system`	Run command in Linux shell on SoC board
`getFile`	Transfer file from SoC board to host computer
`putFile`	Transfer file from host computer to SoC board
`deleteFile`	Delete file on SoC board
`dir`	List directory contents on SoC board
`programFPGA`	Program FPGA and set corresponding device tree from processor on SoC board

Topics

Program Target FPGA Boards or SoC Devices
How to program the target Intel or Xilinx Hardware.
Generate Host Interface Script to Probe and Rapidly Prototype HDL IP Core
Generate host interface script to communicate with the HDL IP core and perform rapid prototyping.
Create Host Interface Script to Control and Rapidly Prototype HDL IP Core
Create and author a host interface script by configuring interfaces and port mapping information to control HDL IP core.
Use JTAG AXI Manager to Control HDL Coder Generated IP Core
This example shows how to specify automatic insertion of the HDL Verifier™ AXI Manager IP into a reference design.
Inspect the Written Values of AXI4 Slave Registers by Using the Readback Methods
This example describes the different techniques to read the AXI4 slave input registers in your design.
Debug IP Core Using FPGA Data Capture
This example shows how to debug an IP core you generate in HDL Coder™ using only FPGA Data Capture as well as both AXI Manager and FPGA Data Capture together.
Model and Debug Test Point Signals with HDL Coder
An example that shows how to add test points to signals in your model and debug these signals in the generated HDL code.