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HDL Code Advisor Checks

The HDL Code Advisor and the Model Advisor checks in HDL Coder™ verify and update your Simulink® model or subsystem for compatibility with HDL code generation. The Code Advisor has checks for:

  • Model configuration settings

  • Ports and Subsystem settings

  • Blocks and block settings

  • Native Floating Point support

  • Industry standard guidelines

When you run a check, the Code Advisor displays the result as a pass or a failure. You can fix warnings or failures by using the Model Advisor recommended settings.

Model configuration checks

Use the checks in this folder to prepare your model for compatibility with HDL code generation. This folder contains checks that verify whether model parameters are HDL-compatible, whether your design contains algebraic loops, and so on.

Check NameDescription

Check for model parameters suited for HDL code generation

Check for model parameters set up for HDL code generation.
Check model for foreign charactersSearch the model for unresolved library links, where the specified library block cannot be found.
Check for global reset setting for Xilinx and Altera devicesCheck asynchronous reset setting for Altera® devices and synchronous reset setting for Xilinx® devices.
Check inline configurations settingCheck whether you have InlineConfigurations enabled.
Check algebraic loopsCheck model for algebraic loops.
Check for visualization settingsCheck model for display settings: port data types and sample time color coding.
Check delay balancing settingCheck Balance Delays is enabled.


If you use the Model Advisor, you see the Check model for foreign characters in the Simulink folder.

Checks for ports and subsystems

This folder contains checks that verify whether ports and subsystems in your model have settings that are compatible for HDL code generation. The checks include whether you have a valid top-level DUT Subsystem and whether you have specified an initial condition for Enabled Subsystem and Triggered Subsystem blocks.

Check NameDescription
Check for invalid top level subsystemCheck for subsystems that cannot be at the top level for HDL code generation.
Check initial conditions of enabled and triggered subsystemsCheck for initial condition of enabled and triggered subsystems.

Checks for blocks and block settings

These checks verify whether blocks in your model are supported for HDL code generation, and whether the supported blocks have HDL-compatible settings. The checks include whether source blocks in your model have a continuous sample time and whether Stateflow® Charts and MATLAB Function blocks have HDL-compatible settings, and so on.

Check NameDescription
Check for infinite and continuous sample time sourcesCheck source blocks with continuous sample time.
Check for unsupported blocksCheck for unsupported blocks for HDL code generation.
Check for large matrix operationsCheck for large matrix operations.
Identify unconnected lines, input ports, and output portsCheck for unconnected lines or ports.
Identify disabled library linksSearch model for disabled library links.
Identify unresolved library linksSearch the model for unresolved library links, where the specified library block cannot be found.
Check for MATLAB Function block settingsCheck HDL compatible settings for MATLAB Function blocks.
Check for Stateflow chart settings

Check HDL compatible settings for Stateflow Chart blocks.

Check Delay, Unit Delay and Zero-Order Hold blocks for rate transitionIdentify Delay, Unit Delay, or Zero-Order Hold blocks that are used for rate transition. Replace these blocks with actual Rate Transition blocks.
Check for blocks that have nonzero output latencyCheck for blocks that have nonzero output latency with fixed point and native floating point.
Check for unsupported storage class for signal objectsCheck whether signal object storage class is 'ExportedGlobal' or 'ImportedExtern' or 'ImportedExternPointer'

Native Floating Point checks

These checks verify whether the model is compatible for HDL code generation in Native Floating Point mode. The checks include whether the blocks in your Simulink model are supported for HDL code generation with Native Floating Point, and whether the model uses single data types, and so on. Native floating-point support in HDL Coder generates target-independent HDL code from your single-precision floating-point model. For more information, see Generate Target-Independent HDL Code with Native Floating-Point.

Check NameDescription
Check for single datatypes in the modelCheck for single data types in the model.
Check for double datatypes in the model with Native Floating PointCheck for double data types in the model.
Check for Data Type Conversion blocks with incompatible settingsCheck conversion mode of Data Type Conversion blocks.
Check for HDL Reciprocal block usageCheck HDL Reciprocal blocks are not using floating point types.
Check for Relational Operator block usageCheck Relational Operator blocks which use floating point types have boolean outputs.
Check for unsupported blocks with Native Floating PointCheck for unsupported blocks with native floating-point.
Check blocks with nonzero ulp errorCheck for blocks that have nonzero ulp error with native floating-point.

industry standard checks

These checks verify whether your Simulink model conforms to the industry-standard rules. industry-standard rules recommend using certain HDL coding guidelines. When generating code, HDL Coder displays an HDL coding standard report that shows how well the generated code adheres to the industry-standard guidelines.

Check NameDescription
Check file extensionCheck file extensions of VHDL files containing entities.
Check naming conventionsCheck standard keywords used by EDA tools.
Check top-level subsystem/port namesCheck top-level module/entity and port names.
Check module/entity namesCheck module/entity names.
Check signal and port namesCheck signal and port name lengths.
Check package file namesCheck file name containing packages.
Check genericsCheck generics at top-level subsystem.
Check clock, reset, and enable signalsCheck naming convention for clock, reset, and enable signals.
Check architecture nameCheck VHDL architecture name in the generated HDL code.
Check entity and architectureCheck whether the VHDL entity and architecture are described in the same file.
Check clock settingsCheck constraints on clock signals.

For more information, see:

See Also

Related Topics