Timing Controller for Multirate Models
A multirate model is model that contains blocks running at multiple sample rates. You can create a multirate model by adding blocks that run at different sample rates or by enabling an HDL optimization, such as streaming, sharing, or clock-rate pipelining, for a single rate model. In a multirate model, HDL Coder™ creates a timing controller entity to define timing signals for the model. These timing signals are signals such as a clock, reset, external clock enable inputs and a clock enable output. A timing controller generates the required rates from a single primary clock by using one or more counters to create multiple clock enables.
In single clock mode:
HDL Coder generates a timing controller if you have a multirate model.
The primary clock rate is the fastest rate in the model.
HDL code generated from multirate models employs a single primary clock input that corresponds to the base rate of the DUT.
In multiple clock mode:
HDL Coder generates a timing controller if the DUT contains downsampling operations that require a clock divider. The outputs of the timing controller are clock enable signals that run at rates that are an integer multiple slower than the timing controller primary clock.
There is no primary clock rate in multiple clock mode.
HDL code generated from multirate models employs one clock input for each rate in the DUT. The number of clock dividers generated in multiple clock mode depends on how many unique downsampling requests there are across various rates.
Timing Controller Naming
The timing controller generates a set of clock enables that contain the necessary rate and phase information to control the clocking for the design in the name of each clock enable. The naming of the clock enables shows the clock enable in relation to the model base rate. The model base rate might not be in the DUT. This naming convention keeps the naming consistent for mapping sample rate colors to the generated HDL code. For information on sample rate colors, see View Sample Time Information.
For example, if the model base rate is not used inside the DUT, the clock in a
timing controller can be labeled as
enb_1_2_0 instead of
enb because the model base rate is the fastest rate in the
model. In this case,
enb_1_2_0 means the model base rate is twice
as fast as the DUT base rate.
Each timing controller entity definition is written to a separate code file. The
timing controller file and entity names are derived from the name of the DUT. To
form the timing controller name, HDL Coder appends the value of the
property to the DUT name. For example, if the name of your DUT is
my_test, in the default case HDL Coder adds the
_tc, to form the timing controller name