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Default System Reference Design for Xilinx SoC Device

The HDL Coder™ software can generate an IP core with an AXI4 or an AXI4-Lite interface. You can integrate the HDL IP core into the Default system reference design.

The Default system is a basic reference design that contains an ARM processor and the HDL IP core. HDL Coder generates the HDL DUT IP core, and inserts it into the reference design. The processor acts as master, and the IP core acts as slave. By accessing the generated registers via the AXI4-Lite interface, the processor can read and write data to and from the IP core. You can tune the parameters on the FPGA, or probe the results from the FPGA via the AXI4-Lite interface in the IP core. To tune the parameters or probe results, use this reference design with External mode in Simulink®.

To specify the Default system as the target reference design:

  1. Specify IP Core Generation as target workflow. Open the HDL Workflow Advisor. In the Set Target Device and Synthesis Tool task, specify IP Core Generation as the Target workflow.

  2. Specify Default system as target reference design. In the Set Target Reference Design task, for Reference design, select Default system. You can also specify whether the code generator inserts the AXI manager IP and the data capture IP for the JTAG or Ethernet connection into the reference design.


    • AXI manager and FPGA data capture in the HDL Workflow Advisor support programmable logic (PL) Ethernet only. The processing system (PS) Ethernet is not supported.

    • By default, the Ethernet option for the Insert AXI Manager (HDL Verifier required) and FPGA Data Capture (HDL Verifier required) parameters is available for these boards.

      • Artix®-7 35T Arty

      • Kintex®-7 KC705

      • Virtex®-7 VC707 (for AXI manager only)

      To enable this option for other Xilinx® boards that have the Ethernet physical layer (PHY), manually add the Ethernet media access controller (MAC) Hub IP in the plugin_board file using the addEthernetMACInterface method before you launch the HDL Workflow Advisor tool.

    • FPGA data capture in the HDL Workflow Advisor does not support SGMII interface.

    For an example of automatic insertion of the AXI manager IP for the JTAG connection into a reference design, see Use JTAG AXI Manager to Control HDL Coder Generated IP Core.

Go through the workflow to generate the HDL IP core, and integrate the IP core into the Default system reference design.

Board Support

You can use the Default system reference design architecture with these target platforms:

  • Xilinx Zynq® ZC702 evaluation kit

  • Xilinx Zynq ZC706 evaluation kit

  • ZedBoard™

  • Xilinx Versal® AI Core Series VCK190 Evaluation Kit.

  • Xilinx Zynq UltraScale+™ MPSoC ZCU102 evaluation kit

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