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Supported EDA Tools and Hardware

Cosimulation Requirements

To get started, see Set Up MATLAB-HDL Simulator Connection or Start HDL Simulator for Cosimulation in Simulink.

Cadence Xcelium Requirements

MATLAB® and Simulink® support Cadence® verification tools using HDL Verifier™. Only the 64-bit version of Incisive® is supported for cosimulation. Use one of these recommended versions, which have been fully tested against the current release:

  • Xcelium™ 19.03

The HDL Verifier shared libraries (liblfihdls*.so, liblfihdlc*.so) are built using the gcc included in the Cadence Incisive® simulator platform distribution. Before you link your own applications into the HDL simulator, first try building against this gcc. See the HDL simulator documentation for more details about how to build and link your own applications.

Mentor Graphics Questa and ModelSim Usage Requirements

MATLAB and Simulink support Mentor Graphics® verification tools using HDL Verifier. Use one of the following recommended versions. Each version has been fully tested against the current release:

  • Questa® Core/Prime 2020.4

  • ModelSim® PE 2020.4

Note

HDL Verifier does not support these versions of ModelSim:

  • ModelSim ME

  • ModelSim-Intel® FPGA Edition

  • ModelSim-Intel Starter Edition

  • QuestaSim-Intel FPGA Edition

  • QuestaSim-Intel Starter Edition

FPGA Verification Requirements

Xilinx Usage Requirements

MATLAB and Simulink support Xilinx® design tools using HDL Verifier. Use the FPGA-in-the-loop (FIL) tools with these recommended versions:

  • Xilinx Vivado® 2020.1

  • Xilinx ISE 14.7

    Note

    Xilinx ISE is required for FPGA boards in the Spartan®-6, Virtex®-4, Virtex-5, and Virtex-6 families.

For tool setup instructions, see Set Up FPGA Design Software Tools.

Intel Quartus Usage Requirements

MATLAB and Simulink support Intel design tools using HDL Verifier. Use the FIL tools with these recommended versions:

  • Intel Quartus® Prime 18.1

  • Intel Quartus Prime Pro 20.2 (supported for Intel Cyclone® 10 GX only)

  • Intel Quartus II 13.1 (supported for Intel Cyclone III boards only)

For tool setup instructions, see Set Up FPGA Design Software Tools.

Microsemi Usage Requirements

MATLAB and Simulink support Microsemi® design tools using HDL Verifier. Use the FIL tools with these recommended versions:

  • Microsemi Libero® SoC v12.0

For tool setup instructions, see Set Up FPGA Design Software Tools.

Supported FPGA Board Connections for FIL Simulation

For board support, see Supported FPGA Devices for FPGA Verification.

Additional boards can be custom added with the FPGA Board Manager. See Supported FPGA Device Families for Board Customization.

JTAG Connection

VendorRequired HardwareRequired Software
Intel

USB Blaster I or USB Blaster II download cable

  • USB Blaster I or II driver

  • For Windows® operating systems: Quartus Prime executable directory must be on system path.

  • For Linux® operating systems: versions below Quartus II 13.1 are not supported. Quartus II 14.1 is not supported. Only 64-bit Quartus is supported. Quartus library directory must be on LD_LIBRARY_PATH before starting MATLAB. Prepend the Linux distribution library path before the Quartus library on LD_LIBRARY_PATH. For example, /lib/x86_64-linux-gnu:$QUARTUS_PATH.

Xilinx

Digilent® download cable.

  • If your board has an onboard Digilent USB-JTAG module, use a USB cable.

  • If your board has a standard Xilinx 14 pin JTAG connector, use with HS2 or HS3 cable from Digilent.

  • For Windows operating systems: Xilinx Vivado executable directory must be on system path.

  • For Linux operating systems: Digilent Adept2

FTDI USB-JTAG cable

  • Supported for boards with onboard FT4232H, FT232H, or FT2232H devices implementing USB-to JTAG

Install these D2XX drivers.

  • For Windows operating systems: 2.12.28 (64 bit)

  • For Linux operating systems: 1.4.22 (64 bit)

For the installation guide, see D2XX Drivers from the FTDI Chip website.

MicrosemiJTAG connection not supported

Note

When simulating your FPGA design through Digilent JTAG cable with Simulink or MATLAB, you cannot use any debugging software that requires access to the JTAG; for example, Vivado Logic Analyzer.

Ethernet Connection

Required HardwareSupported Interfaces[a]Required Software
  • Gigabit Ethernet card

  • Cross-over Ethernet cable

  • FPGA board with supported Ethernet connection

  • Gigabit Ethernet — GMII

  • Gigabit Ethernet — RGMII

  • Gigabit Ethernet — SGMII

  • Ethernet — MII

  • Ethernet — RMII

There are no software requirements for an Ethernet connection, but ensure that the firewall on the host computer does not prevent UDP communication.

[a] The HDL Verifier Support Package for Microsemi FPGA Boards supports only SGMII interfaces.

Note

  • RMII is supported with Vivado versions older than 2019.2.

  • Ethernet connection to Virtex-7 VC707 not supported for Vivado versions older than 2013.4.

Supported FPGA Devices for FPGA Verification

HDL Verifier supports FIL simulation, FPGA data capture, and MATLAB AXI master on the devices shown in the following table. The board definition files for these boards are in the Download FPGA Board Support Package. You can add other FPGA boards for use with FIL, FPGA data capture, and MATLAB AXI master with FPGA board customization (FPGA Board Customization).

Device FamilyBoardEthernetJTAGPCI ExpressComments
FILFPGA Data CaptureMATLAB AXI MasterFILFPGA Data CaptureMATLAB AXI MasterFIL[a]FPGA Data CaptureMATLAB AXI Master

Xilinx Artix®-7

Digilent Nexys™ 4 Artix-7

x  xxx    
Digilent Arty Boardxxxxxx    

Xilinx Kintex®-7

Kintex-7 KC705xxxxxxx   

Xilinx Kintex UltraScale™

Kintex UltraScale FPGA KCU105 Evaluation Kit

xxxxxx    

Xilinx Kintex UltraScale+™

Kintex UltraScale+ FPGA KCU116 Evaluation Kit

 xxxxx  xFor more information, see PCI Express MATLAB AXI Master (HDL Verifier Support Package for Xilinx FPGA Boards).

Xilinx Spartan-6

Spartan-6 SP605xxx       
Spartan-6 SP601xxx       
XUP Atlys Spartan-6xxx       

Xilinx Spartan-7

Digilent Arty S7-25   xxx    

Xilinx Virtex UltraScale

Virtex UltraScale FPGA VCU108 Evaluation Kit

xxxxxx    

Xilinx Virtex UltraScale+

Virtex UltraScale+ FPGA VCU118 Evaluation Kit

 xxxxxx   

Xilinx Virtex-7

Virtex-7 VC707xxxxxxx   
Virtex-7 VC709   xxxx   

Xilinx Virtex-6

Virtex-6 ML605xxx       

Xilinx Virtex-5

Virtex ML505xxx       
Virtex ML506xxx       
Virtex ML507xxx       
Virtex XUPV5–LX110Txxx       

Xilinx Virtex-4

Virtex ML401xxx      

Note

Support for Virtex-4 device family will be removed in a future release.

Virtex ML402xxx      
Virtex ML403xxx      

Xilinx Zynq®

Zynq-7000 ZC702

   xxx    
Zynq-7000 ZC706   xxxx    
ZedBoard™  xxxx   Use the USB port marked "PROG" for programming.

ZYBO™ Zynq-7000 Development Board

   xxx    
PicoZed™ SDR Development Kit   xxx    
MiniZed™    xx    

Xilinx Zynq UltraScale+

Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit

   xxx    

Zynq UltraScale+ MPSoC ZCU104 Evaluation Kit

   xxx    

Zynq UltraScale+ MPSoC ZCU106 Evaluation Kit

   xxx    

Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit

   xxx    

Zynq UltraScale+ RFSoC ZCU216 Evaluation Kit

   xxx    

Intel Arria® II

Arria II GX FPGA Development Kitx  xxx    

Intel Arria V

Arria V SoC Development Kit   xxx    
Arria V Starter Kitx  xxx    

Intel Arria 10

Arria 10 SoC Development Kitx  xxx   

For Ethernet connection, use Quartus Prime 16.1 or newer.

Arria 10 GXx  xxxx x

For Ethernet connection, use Quartus Prime 16.1 or newer.

Quartus Prime 18.0 is not recommended for Arria 10 GX over PCI Express®.

Intel Cyclone IV

Cyclone IV GX FPGA Development Kitx  xxx   
DE2-115 Development and Education Boardx  xxx   The Altera® DE2-115 FPGA development board has two Ethernet ports. FIL uses only Ethernet 0 port. Make sure that you connect your host computer with the Ethernet 0 port on the board via an Ethernet cable.
BeMicro SDKx  xxx    

Intel Cyclone III

Cyclone III FPGA Starter Kit   xxx   

Altera Cyclone III boards are supported with Quartus II 13.1

Note

Support for Cyclone III device family will be removed in a future release.

Cyclone III FPGA Development Kitx  xxx   
Altera Nios II Embedded Evaluation Kit, Cyclone III Editionx  xxx   

Intel Cyclone V

Cyclone V GX FPGA Development Kitx  xxx    
Cyclone V SoC Development Kit    xxx    
Cyclone V GT Development Kitx  xxxx   
Terasic Atlas-SoC Kit / DE0-Nano SoC Kit   xxx    
Arrow® SoCKit Development Kit   xxx    

Intel Cyclone 10 LP

Altera Cyclone 10 LP Evaluation Kit

   xxx    

Intel Cyclone 10 GX

Altera Cyclone 10 GX FPGA Evaluation Kit

   xxx   

Must be used with Quartus Prime Pro.

Intel MAX® 10

Arrow MAX 10 DECA

x xxxx    

Intel Stratix® IV

Stratix IV GX FPGA Development Kitx  xxx    

Intel Stratix V

DSP Development Kit, Stratix V Edition
x  xxxx   

Microsemi SmartFusion®2

Microsemi SmartFusion2 SoC FPGA Advanced Development Kit

x        See Installing Microsemi SmartFusion2 SoC FPGA Advanced Development Kit (HDL Verifier Support Package for Microsemi FPGA Boards).

Microsemi Polarfire®

Microsemi Polarfire Evaluation Kit

x        See Installing Microsemi Polarfire Evaluation Kit (HDL Verifier Support Package for Microsemi FPGA Boards).

Microsemi RTG4®

RTG4-DEV-KIT

x         

[a] FIL over PCI Express connection is supported only for 64-bit Windows operating systems.

Limitations

  • For FPGA development boards that have more than one FPGA device, only one such device can be used with FIL.

FPGA Board Support Packages.  The FPGA board support packages contain the definition files for all supported boards. You can download one or more vendor-specific packages. To use FIL, download at least one of these packages, or customize your own board definition file. See Create Custom FPGA Board Definition.

To see the list of HDL Verifier support packages, visit HDL Verifier Supported Hardware. To download an FPGA board support package:

  • On the MATLAB Home tab, in the Environment section, click Add-Ons > Get Hardware Support Packages.

Supported FPGA Device Families for Board Customization

HDL Verifier supports the following FPGA device families for board customization; that is, when you create your own board definition file. See FPGA Board Customization. PCI Express is not a supported connection for board customization.

Note

The HDL Verifier Support Package for Microsemi FPGA Boards does not support board customization.

Device FamilyRestrictions
Xilinx Artix 7 
Kintex 7 

Kintex UltraScale

 

Kintex UltraScale+

 
Spartan 6

Ethernet PHY RGMII is not supported.

Spartan 7 
Virtex 4

Note

Support for Virtex-4 device family will be removed in a future release.

Virtex 5 
Virtex 6 
Virtex 7

Supports Ethernet PHY SGMII only.

Virtex UltraScale

 

Virtex UltraScale+

 
Zynq 7000 

Zynq UltraScale+

 
Intel Arria II 
Arria V 
Arria 10  
Cyclone III

Note

Support for Cyclone III device family will be removed in a future release.

Cyclone IV 
Cyclone V 
Cyclone 10 LP 
Cyclone 10 GX 
MAX 10  
Stratix IV 
Stratix V 

UVM and DPI Component Generation Requirements

UVM and DPI component generation supports the same versions of Cadence Incisive and Mentor Graphics Questa and ModelSim as for cosimulation. You can generate a DPI component for use with either 64-bit or 32-bit Incisive.

In addition, UVM and DPI Component generation also supports:

  • Synopsys® VCS® MX O-2018.09 SP2

Note

When you run a DPI component in ModelSim 10.5b on Debian® 8.3, you may encounter a library incompatibility error:

** Warning: ** Warning: (vsim-7032) The 64-bit glibc RPM 
does not appear to be installed on this machine.  Calls to gcc may fail.
** Fatal: ** Error: (vsim-3827) Could not compile 'STUB_SYMS_OF_fooour.so':
To avoid this issue, on the Code Generation pane in Configuration Parameters, try these options:

  • Set the Build configuration to Faster Runs.

  • Or, set the Build configuration to Specify and specify the compiler flag -O3.

UVM generation also requires a UVM Reference Implementation, available for download from the UVM standard website. This feature is tested with the default shipped version for each supported simulator.

TLM Generation Requirements

With the current release, TLMG includes support for:

  • Compilers:

    • Visual Studio®: VS2008, VS2010, VS2012, VS2013, VS2015, and VS2017

    • Windows 7.1 SDK

    • gcc 6.3

  • SystemC:

    • SystemC 2.3.1 (TLM included)

      You can download SystemC and TLM libraries at https://accellera.org. Consult the Accellera Systems Initiative website for information about how to build these libraries after downloading.

  • System C Modeling Library (SCML):

Troubleshooting

When executing the HDL Verifier product examples on a Windows machine there can be errors caused by a Windows path limit of 260 characters. Sometimes the condition can be caught and you may receive an error such as the following:

Build failed because the build file name(s) exceed the Windows limit of 260 characters. Build from a working directory with a shorter path, to allow build files to be created with shorter filenames.

Often, however, the long path is created during the execution of third party tools such as Vivado or Quartus and the resulting error from those tools will seem to be unrelated. Some examples for such errors are:

  • ERROR: [Common 17-680] Path length exceeds 260-Byte maximum allowed by Windows: 
    c:\Users\user\OneDrive - MathWorks\Documents\MATLAB\Examples\R2021b\xilinxfpgaboards\
    ZynqEthernet\ethernetaximasterzynq.srcs\sources_1\bd\design_1\ip\design_1_mig_7series_0_0\
    _tmp\/design_1_mig_7series_0_0/example_design/rtl/traffic_gen/mig_7series_v4_2_axi4_tg.v 
    Please consider using the OS subst command to shorten the path length by mapping part 
    of the path to a virtual drive letter. See Answer Record AR52787 for 
    more information. 
    Resolution: In Windows 7 or later, the mklink command can also be used to create a 
    symbolic link and shorten the path. 

  • WARNING: [Vivado 12-8222] Failed run(s) : 'clk_wiz_0_synth_1', 'simcycle_fifo_synth_1'
    wait_on_run: Time (s): cpu = 00:00:00 ; elapsed = 00:02:16 . 
    Memory (MB): peak = 1636.988 ; gain = 0.000
    # if {[get_property PROGRESS [get_runs synth_1]] != "100%"} {  
    #   error "ERROR: Synthesis failed"
    

  • Error (12006): Node instance "ident" instantiates undefined entity 
    "alt_sld_fab_altera_connection_identification_hub_171_gdd6b5i"
    Ensure that required library paths are specified correctly, 
    define the specified entity, or change the instantiation.
    If this entity represents Intel FPGA or third-party IP,
    generate the synthesis files for the IP.  

A long path may be suspected when the root folder for running the example is already fairly long, such as over 100 characters.

In both the detected and undetected long path scenarios, to avoid the errors, use one of these methods:

  • Map the example directory to a shorter letter drive alias. For example, the following will eliminate 122 characters from the path, allowing much more headroom for the 260 character limit.

    cmd> subst W: “C:\Users\janedoe\OneDrive - Personal\Documents\MATLAB\Examples\R2021b\hdlverifier\GettingStartedWithSimulinkHDLCosimExample”

  • After opening an example, copy the example directory to a directory with a short name (such as /tmp).