generateFPGADataCaptureIP

Open FPGA Data Capture Component Generator

Syntax

generateFPGADataCaptureIP

generateFPGADataCaptureIP('restore',true)

generateFPGADataCaptureIP(matFile)

Description

generateFPGADataCaptureIP opens the FPGA Data Capture Component Generator.

generateFPGADataCaptureIP('restore',true) opens the FPGA Data Capture Component Generator and reloads the parameters of the most recent design.

generateFPGADataCaptureIP(matFile) opens the FPGA Data Capture Component Generator and reloads the parameters of a design you already generated and saved in matFile.

Examples

Launch FPGA Data Capture Component Generator

This example shows how to launch the FPGA Data Capture Component Generator tool.

Open Tool With Default Settings

Run the following command to launch the FPGA Data Capture Component Generator tool:

generateFPGADataCaptureIP

Input Arguments

restore — Option to reload most recent design parameters

false (default) | true

Option to reload the most recent design parameters, specified as true or false. When you specify this input as true, the FPGA Data Capture Component Generator opens and reloads the parameters of the most recent design. Otherwise, the tool opens with default settings.

Example: 'restore',true

Data Types: logical

matFile — MAT file containing design parameters

character vector | string scalar

MAT file containing design parameters, specified as a character vector or string scalar. Specify this input in the form datacapture_gensettings.mat, replacing datacapture with the generated HDL IP core name.

This MAT file is a generated file in the same folder as your other generated data capture components. When you specify this input, the FPGA Data Capture Component Generator opens and reloads the parameters of the design specified by this value.

You must provide only the MAT file name if the file is in the current working folder.

Example: 'datacapture_gensettings.mat'

You must provide the full path to the saved MAT file if the file is not in the current working folder.

Example: 'C:/home/user/datacapture_gensettings.mat'

Data Types: char | string

Version History

Introduced in R2017a

R2023a: Reload previous design parameters

The function reloads the parameters of a design you already generated and saved in a MAT file.

To reload the same design in your next iteration, provide the MAT file containing design parameters as an input argument to the function.

generateFPGADataCaptureIP('datacapture_gensettings.mat');

Where datacapture is the Generated IP name that you specify in the FPGA Data Capture Component Generator tool.