Custom Template Language Syntax

Note

Using SystemVerilog Template (SVT) syntax is not recommended for creating custom template files (since R2025a). Use the target language compiler (TLC) directives instead. For information on updating your code, see Convert SVT Template to TLC.

Template files are SystemVerilog code parameterized to generate different kinds of SystemVerilog DPI components and UVM artifacts. Templates use template directives and template variables to generate components for specific variable values. You can assign variable values from the svdpiConfiguration object properties, local template dictionaries, and design-specific information.

For applications that cannot use built-in template files, you can create a configuration with the ComponentKind property set to custom and write custom template files.

Note

This feature requires the ASIC Testbench for HDL Verifier add-on.

Template Anatomy

A template can first include predefined template variables that defined in other files such as the SystemVerilogTemplateLibrary.tlc. For example:

%include "SystemVerilogTemplateLibrary.tlc"

After defining or including the required template variables, the template specifies the contents of the SystemVerilog artifacts that it generates between %openfile and %closefile directives. The content is composed of SystemVerilog, YAML, and TCL code, and also bash and shell scripts. The generated files include the template variables defined in the local dictionary or included in the file. At run time, the target language compiler assigns your values to these template variables and replaces them with SystemVerilog text. For example, the top part of the combinational module template has this structure:

%openfile sv_file = "%<gtd.ComponentTypeName>.sv"
// -------------------------------------------
// File:    %<gtd.ComponentTypeName>.sv
%<SVTLCommonHeader>

`timescale 1ns/1ns

import %<gtd.ComponentPackageTypeName>::*;

module %<gtd.ComponentTypeName> (
%foreach io = ptd.ALL_INS_AND_OUTS_size
    %<ptd.ALL_INS_AND_OUTS[io].PORT_DECL>%<ptd.ALL_INS_AND_OUTS[io].PORT_COMMA>
%endforeach
);
.
.
.

endmodule
%closefile sv_file

When the ComponentTypeName is sineWaveGen the engine generates the output into a file named sineWaveGen.sv as indicated by the %openfile and %closefile directives.

For an example, see Generate SystemVerilog DPI Component from MATLAB Function.

// -------------------------------------------
// File:    sineWaveGen.sv

// -------------------------------------------
// Created: 03-Jan-2023 19:04:05
// Tools  : Generated by MATLAB 9.14 and HDL Verifier 7.1

// -------------------------------------------

`timescale 1ns/1ns
import sineWaveGen_pkg::*;

module sineWaveGen (
  input real amp  ,
  input real freq  ,
  output real y [0:99]
);
.
.
.
endmodule

Template Directives

Template directives provide instructions for the target language compiler to generate files, iterate on port groups, define and use variables, and emit SystemVerilog code.

For full list of target language directives, see Target Language Compiler Directives (Simulink Coder).

Template Variables

When processing a template, HDL Verifier™ replaces template variables with values. Most variable values are the result of entries in a global and local dictionary. This table describes the predefined variables in the system in their lookup order. You can build your own library of variable definitions with custom dictionaries.

Variable Source	Variables
Global dictionary This dictionary is defined in the svdpiConfiguration object. It reflects the property values that you set in addition to the dictionary defined by the TemplateDictionary property.	gtd.ComponentKind gtd.ComponentTypeName gtd.TestBenchTypeName gtd.ComponentTemplateFiles gtd.TestBenchTemplateFiles gtd.MATLABTestBenchFunctionName gtd.MATLABFunctionName gtd.DLLOutputName TemplateDictionary contents
Port dictionary There are several built-in port groups and you can define your own groups using the PortGroups property of the svdpiConfiguration object. In a %foreach / %endforeach template block, you can define several template variables specific to the port in each iteration. For example: %foreach io = ptd.ALL_PORTS_size %<ptd.ALL_PORTS[io].PORT_DECL>%<ptd.ALL_PORTS[io].PORT_COMMA> %endforeach	Built-in port groups ptd.ALL_PORTS ptd.ALL_INPUTS ptd.ALL_OUTPUTS ptd.ALL_SEQ_CONTROL ptd.ALL_INS_AND_OUTS ptd.ALL_FIELD_MACRO_INPUTS ptd.ALL_FIELD_MACRO_OUTPUTS ptd.ALL_VARSIZE_OUTPUTS ptd.ALL_NONVARSIZE_OUTPUTS ptd.ALL_VARSIZE_INPUTS ptd.ALL_BOUNDED_VARSIZE_INPUTS ptd.ALL_NONVARSIZE_INPUTS ptd.ALL_TESTPOINTS ptd.ALL_PARAMETERS ptd.ALL_INPUTS_WITH_CONSTRAINTS ptd.ALL_REAL_PARAMETERS_WITH_CONSTRAINTS ptd.ALL_NONREAL_PARAMETERS_WITH_CONSTRAINTS Built-in variables for each port PORT_NAME PORT_DIRECTION PORT_DATATYPE PORT_DIMENSIONS PORT_RAND_QUALIFIER PORT_FIELD_MACRO_TYPE PORT_DECL PORT_VAR_DECL PORT_RAND_VAR_DECL PORT_FIELD_MACRO_DECL PORT_COMMA – Use this variable to accommodate constructs such as function argument lists that requires a comma between arguments but no comma after the last one. The value for this variable is empty for the last port in a port group, otherwise the value is ','. Convenience variables for iteration <ptd.PortGroup>_size
Local dictionaries HDL Verifier provides a special dictionary, SystemVerilogTemplateLibrary, which you can include in a template using: %include SystemVerilogTemplateLibrary.tlc	General Variables: SVTLCommonHeader SVTLDPIPackageDefinition SVTLAllModuleScripts SVTLAllUVMScripts Variables specific to Questa™ simulator: SVTLQuestaDoFileStart SVTLQuestaDoFileWaves SVTLQuestaModuleDoFile SVTLQuestaModuleToolchainDoFile SVTLQuestaUVMDoFile SVTLQuestaUVMToolchainDoFile Variables specific to Xcelium™ simulator: SVTLXceliumScriptFileStart SVTLXceliumModuleScript SVTLXceliumModuleToolchainScript SVTLXceliumUVMScript SVTLXceliumUVMToolchainScript Variables specific to VCS® simulator: SVTLVCSScriptFileStart SVTLVCSModuleScript SVTLVCSModuleToolchainScript SVTLVCSUVMScript SVTLVCSUVMToolchainScript Variables specific to Vivado® simulator: SVTLVivadoScriptFileStart SVTLVivadoModuleScript SVTLVivadoModuleToolchainScript SVTLVivadoUVMScript SVTLVivadoUVMToolchainScript SVTLVivadoScriptFileStartWin SVTLVivadoModuleScriptWin SVTLVivadoModuleToolchainScriptWin SVTLVivadoUVMScriptWin SVTLVivadoUVMToolchainScriptWin
Built-in variables These variables are built-in.	gtd.HasVarSizeInputs gtd.HasVarSizeOutputs gtd.TimeStamp gtd.ToolVersions gtd.IsUsingHDLToolchain gtd.IsCrossPlatformWorkflow gtd.IsQuestaSimToolchain gtd.IsXceliumToolchain gtd.IsVCSToolchain gtd.IsVivadoToolchain gtd.DPIObjectHandleDecl gtd.ResetFcnCallStart gtd.OutputFcnCallStart gtd.CalcAndSizesFcnCallStart gtd.VarSizeOutputFcnCallStart gtd.TestBenchVectorGetAndCheck

Convert SVT Template to TLC

If you have custom templates for generating SystemVerilog DPI or UVM components from MATLAB^®, convert them to use Target Language Compiler (Simulink Coder). Identify the structure of the SVT file. Then, analyze the sections of the template, such as file headers, class definitions, and code blocks.

1. To access the built-in global and port dictionary, include the SystemVerilogTemplateLibrary.tlc library.

2. Convert SVT directives to TLC directives. For example:

   • To create files, use %openfile %closefile.

   • For iterative loops, use %foreach %endforeach.

   • For comments, use /%...%/ or %%.

   • To assign local variables, specify var=value.

3. Use the global dictionary when available. It uses the same variable names but adds a prefix of gtd. See Template Variables for global variables.

4. Use the port dictionary. It uses the same variable names but adds a prefix of ptd. See Template Variables for port variables.

5. Use the built-in templates located in this folder as a reference:

   <matlabroot>\toolbox\hdlverifier\dpigenerator\rtw