|ID: Title||hisl_0013: Usage of data store blocks|
|Description||To support deterministic behavior across different sample times or models when using data store blocks, including Data Store Memory, Data Store Read, and Data Store Write:|
In the Configuration
Parameters dialog, on the Diagnostics > Data Validity pane, set these Data Store Memory
Using data store memory blocks can have significant impact on your software verification effort. Models and subsystems that use only inports and outports to pass data provide a directly traceable interface, simplifying the verification process.
In addition to the diagnostics, you can more accurately detect data store memory access violations in your model using Simulink® Design Verifier™. To do this, on the Design Verifier tab, select Settings. In the Configuration Parameters dialog box, on the Design Verifier > Design Error Detection pane, select Data store access violations. For more information, see Detect Data Store Access Violations in a Model (Simulink Design Verifier). A Simulink Design Verifier license is required.
Support consistent data values across different sample times or models.
Prevent unintended data corruption.
|Model Advisor Checks||Check safety-related diagnostic settings for data store memory (Simulink Check)|
The following examples use Rate Transition blocks to provide deterministic data transfer between different rates and tasks.
For fast-to-slow transitions:
Set the rate of the slow sample time on either the Rate Transition block or the Data Store Write block.
Do not place the Rate Transition block after the Data Store Read block.
For slow-to-fast transitions:
If the Rate Transition block is after the Data Store Read block, specify the slow rate on the Data Store Read block.
If the Rate Transition block is before the Data Store Write block, use the inherited sample time for the blocks.
|ID: Title||hisl_0015: Usage of Merge blocks|
To support unambiguous behavior from Merge blocks,
Use Merge blocks only with conditionally executed subsystems.
Specify execution of the conditionally executed subsystems such that only one subsystem executes during a time step.
Clear block parameter Allow unequal port widths.
|D||Set the Outport block parameter
Output when disabled to
Simulink combines the inputs of the Merge block into a single output. The output value at any time is equal to the most recently computed output of the blocks that drive the Merge block. Therefore, the Merge block output is dependent upon the execution order of the input computations.
To provide predictable behavior of the Merge block output, you must have mutual exclusion between the conditionally executed subsystems feeding a Merge block.
parameter Allow unequal port widths is only
available when configuration parameter Underspecified
initialization detection is set to
|Rationale||A, B, C, D||Avoid unambiguous behavior.|
|Model Advisor Checks||Check usage of Merge blocks (Simulink Check)|
Merge block in the Simulink documentation
|ID: Title||hisl_0021: Consistent vector indexing method|
|Description||Within a model, use:|
Consistent vector indexing method.
Supports configurable indexing:
Support only one-based indexing:
Supports only zero-based indexing:
|Rationale||A||Reduce the risk of introducing errors due to inconsistent indexing.|
|Model Advisor Checks||Check for inconsistent vector indexing methods (Simulink Check)|
|See Also||cgsl_0101: Zero-based indexing|
|ID: Title||hisl_0022: Data type selection for index signals|
|Description||For index signals, use:|
|A||An integer or enumerated data type|
|B||A data type that covers the range of indexed values.|
Blocks that use a signal index include:
|Rationale||A||Prevent unexpected results that can occur with rounding operations for floating-point data types.|
|B||Enable access to data in a vector.|
|Model Advisor Checks||Check data types for blocks with index signals (Simulink Check)|
|ID: Title||hisl_0023: Verification of variant blocks|
|Description||When verifying that a model is consistent with generated code, do the following:|
|A||For each Variant Model block, clear block parameter Generate preprocessor conditionals.|
|B||For each Variant
Subsystem block, set the Variant
activation time to |
|C||Verify combinations of model variants that might be active in the generated code.|
|Rationale||A,B||Simplify consistency testing between the model and generated code by restricting the code base to a single variant.|
|C||Verify that consistency testing between the model and generated code is complete for variants.|
|Model Advisor Checks||Check usage of variant blocks (Simulink Check)|
|ID: Title||hisl_0034: Usage of Signal Routing blocks|
When using Switch
blocks, avoid comparisons using the
Due to floating-point precision
issues, do not test floating-point expressions for inequality
When the model contains a
Switch block computing a relational operator with the
Improve model robustness.
|Model Advisor Checks||Check usage of Signal Routing blocks (Simulink Check)|