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Bonnes pratiques pour une analyse Simulink Design Verifier
Bonnes pratiques, hypothèses et limites de support pour une analyse Simulink® Design Verifier™
Simulink Design Verifier propose différents niveaux de support pour les fonctionnalités Simulink. Si votre modèle contient des blocs partiellement supportés, vous pouvez activer la suppression automatique ou éviter d’utiliser des fonctionnalités non supportées dans les modèles que vous analysez.
Rubriques
Bonnes pratiques et hypothèses
- Simulink Design Verifier Block Library
- Handle Model Complexities with Automatic Stubbing
How Simulink Design Verifier uses automatic stubbing to handle model complexities. - Modified Condition and Decision Coverage in Simulink Design Verifier
Describes the difference between MCDC coverage in Simulink Design Verifier and in Simulink Coverage™. - Enhanced MCDC Coverage in Simulink Design Verifier
Describes the Enhanced MCDC coverage concept and workflows. - Analyze Model for Enhanced MCDC Analysis
Analyze a model for enhanced MCDC objectives. - Logical Operations Short-circuiting
Explains how Simulink Design Verifier short-circuits logic blocks. - Understanding Result Approximations
Simulink Design Verifier identifies and reports approximation during analysis.
Détails concernant les limites de support
- Limitations of Simulink Design Verifier for Simulink Software Features
Review Simulink software features that Simulink Design Verifier does not support. - Unsupported Simulink Blocks in Analysis
Review Simulink blocks that Simulink Design Verifier does and does not support. - Analysis Limitations and Considerations for Model Blocks
Review Simulink Design Verifier limitations for the Model block. - Limitations of Simulink Design Verifier with Stateflow Features
Lists the Stateflow® software features that the Simulink Design Verifier and Fixed-Point Designer™ software does not support. - Simulink Design Verifier Limitations for MATLAB for Code Generation
Review limitations associated with Simulink Design Verifier software support for MATLAB® for code generation. - Simulink Design Verifier Limitations and Considerations for S-Functions and C/C++ Code
Lists limitations and considerations of S-functions and Generated Code in Simulink Design Verifier. - Analyze Models with Counters and Timers
Best practices for handling counters and timers in your model to avoid over complicating Simulink Design Verifier analysis. - Logical Operations Short-circuiting
Explains how Simulink Design Verifier short-circuits logic blocks.
