Assess Model Simulation Using verify Statements

You can verify model simulation by including a Test Assessment block in your model or test harness, and authoring verify statements in the Test Assessment block. verify statements return pass, fail, or untested results for both the overall simulation and individual time steps. Results appear in the Test Manager.

Activate verify Statements in the Test Assessment Block

The Test Assessment contains a When decomposition sequence. The When decomposition sequence helps you clearly define the simulation condition that activates each verify statement:

1. If your model uses a Test Sequence block source, consider activating each verify statement using the active Test Sequence block step.

2. If your model does not use a Test Sequence block source, or your test sequence steps do not correspond with conditions to verify, activate each verify statement using a signal condition.

Activate verify Statements with Test Sequence Steps

Connect the Test Sequence and Test Assessment block with the active step signal from the Test Sequence block. Activate each verify statement with the active step.

For example, this test harness contains a Test Sequence and Test Assessment block. The blocks are connected by the Active_Step signal.

The Test Assessment block contains a when decomposition sequence with four substeps. Each contains a verify statement and is activated with a different Test Sequence block step.

The Else step in this example has no actions and handles simulation conditions that do not match any of the preceding when conditions. The name of such a step can be Else or any other desired name. This step cannot contain a when condition.

To activate verify statements in a Test Assessment with active steps in a Test Sequence block:

1. Create active step data output for the Test Sequence block.

   1. Select the Test Sequence block.

      Create a new enumerated data output. In the Property Inspector, select Create data to monitor the active step and set the Data Type to Enum.

   2. Enter a name in Enum name.

      

2. Create a data input for the Test Assessment block:

   1. Open the Test Assessment block.

   2. In the Symbols pane, hover next to Input, then click Add data .

   3. Name the input.

3. In the block diagram, connect the Test Sequence block output to the Test Assessment block input.

4. Create a When decomposition sequence in the Test Assessment block.

   1. The Test Assessment block is configured by default with a When decomposition sequence. To change between a standard sequence and a When decomposition sequence, right-click the parent step and select When decomposition.

   2. For each When decomposition step, define when the step is active by using the active step enumeration data. For example:

      VerifyBoth when TSActiveStepIN == ...
         Test_Sequence_Active_Step_Enum.PressBothButtons

   3. Add verify statements to each assessment step.

Activate verify Statements with Signal Conditions

If your model does not use a Test Sequence block source, or if Test Sequence steps do not correspond with conditions to verify, use unique signal conditions to activate verify statements. Place verify statements in a When decomposition sequence, and use conditional statements in the When conditions.

For example, this test harness uses a Signal Editor block input.

The Test Assessment block contains a When decomposition sequence. Each substep contains a verify statement. A unique signal condition activates each substep.

Author verify Statements

verify statements evaluate logical expressions. You can label results in the Test Manager with optional arguments.

A verify statement returns a pass, fail, or untested result for each time step and for the overall simulation. A fail at any time step results in an overall fail. If there are no failing results, a pass at any time step results in an overall pass. Otherwise, the overall result is untested. Results appear in the Verify Statements section of the test results. For details on verify syntax and considerations for using it, see the verify reference page.

Example

In this comparison of two values, the parent step uses verify statements to assess two local variables x and y during the simulation.

• verify(x >= y) passes overall because it is true for the entire test sequence.

• verify(x == y) and verify(x ~= y) fail because they fail in step_1_2 and step_1_1, respectively.

The Test Manager displays the results: