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System object: hdlverifier.FPGADataReader
Package: hdlverifier

Configure each signal value comparison, as a part of overall trigger condition




setTriggerCondition(DC,name,enable,value) specifies a trigger value comparison for a signal, name. The enable argument indicates whether this signal is part of the overall trigger condition.

Input Arguments

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This object is the customized object you created using the FPGA Data Capture Component Generator app.

Specify a signal name matching one that you configured when you generated the object. The signal must be configured as a possible trigger signal.

To use this signal in the overall trigger condition, set this argument to true. When you set this argument to false, this signal is not used for the overall trigger condition.

The trigger condition can be composed of value comparisons of one or more signals. This parameter specifies the value to match for each signal. For a multibit signal, specify a numeric value. For Boolean signals, specify a string that indicates the level or edge to match. See Triggers.