This example shows how the GPU Coder™ Support Package for NVIDIA® GPUs enables the GPU Coder product to run PIL execution on NVIDIA® DRIVE™ and Jetson hardware platforms. This example uses the GPU Code generation for fog rectification example from GPU Coder to demonstarte PIL execution. For more information, see Fog Rectification.
Target Board Requirements
NVIDIA Jetson or DRIVE embedded platform.
Ethernet crossover cable to connect the target board and host PC (if the target board cannot be connected to a local network).
NVIDIA CUDA toolkit installed on the board.
Environment variables on the target for the compilers and libraries. For more information, see Install and Setup Prerequisites for NVIDIA Boards.
Development Host Requirements
GPU Coder for CUDA code generation. For a tutorial, see Get Started with GPU Coder.
Image Processing Toolbox™.
Embedded Coder™ for code generation.
NVIDIA CUDA toolkit on the host.
GPU Coder Interface for Deep Learning Libraries support package. To install this support package, use the MATLAB®
The following line of code creates a folder in your current working folder on the host and copies all the relevant files into this folder. If you cannot generate files in this folder, before running this command, change your current working folder.
The GPU Coder Support Package for NVIDIA GPUs uses an SSH connection over TCP/IP to execute commands while building and running the generated CUDA code on the DRIVE or Jetson platforms. Connect the target platform to the same network as the host computer or use an Ethernet crossover cable to connect the board directly to the host computer. For information on how to set up and configure your board, see NVIDIA documentation.
To communicate with the NVIDIA hardware, create a live hardware connection object by using the
jetson function. You must know the host name or IP address, user name, and password of the target board to create a live hardware connection object. For example, when connecting to the target board for the first time, create a live object for Jetson hardware by using the command:
hwobj = jetson('jetson-tx2-name','ubuntu','ubuntu');
During the hardware live object creation, the support package performs hardware and software checks, IO server installation, and gathers peripheral information on target. This information is displayed in the Command Window.
Similarly, to create live object for DRIVE hardware, use the command:
hwobj = drive('drive-px2-name','ubuntu','ubuntu');
In case of a connection failure, a diagnostics error message is reported at the MATLAB command line. If the connection has failed, the most likely cause is incorrect IP address or host name.
To verify that the compilers and libraries necessary for running this example are set up correctly, use the
envCfg = coder.gpuEnvConfig('jetson'); % Use 'drive' for NVIDIA DRIVE hardware envCfg.BasicCodegen = 1; envCfg.Quiet = 1; envCfg.HardwareObject = hwobj; coder.checkGpuInstall(envCfg);
To run PIL execution NVIDIA target, create a GPU code configuration object for 'lib' and set verification mode to 'PIL'.
cfg = coder.gpuConfig('lib'); cfg.VerificationMode = 'PIL';
To create a configuration object for the DRIVE or Jetson platform and assign it to the
Hardware property of the code configuration object
cfg, use the
coder.hardware function. Use
'NVIDIA Jetson' for the Jetson TX1 or TX2 boards and
'NVIDIA Drive' for the DRIVE board.
cfg.Hardware = coder.hardware('NVIDIA Jetson');
To enable code execution profiling, set
CodeExecutionProfiling of the GPU Coder configuration object to true.
cfg.CodeExecutionProfiling = true;
Load sample foggy input image.
foggyImg = imread('foggyInput.png');
To generate CUDA code, use the
codegen function and pass the GPU code configuration and the size of the inputs for
fog_rectification entry-point function. The code generator creates a
MEX function named
fog_rectification_pil for PIL-based execution.
To run the generated code on the target board and get the results into MATLAB, call the
fog_rectification_pil MEX function with required input.
defoggyImg_pil = fog_rectification_pil(foggyImg);
p1 = subplot(1, 2, 1); p2 = subplot(1, 2, 2); imshow(foggyImg, 'Parent', p1); imshow(defoggyImg_pil, 'Parent', p2); title(p1, 'Foggy Input Image'); title(p2, 'Defogged Output Image from Hardware');
To verify the numeric accuracy of the generated code, compare MATLAB results to those from the PIL execution.
defoggyImg_sim = fog_rectification(foggyImg); diffImg = defoggyImg_sim - defoggyImg_pil; fprintf('The maximum difference between the PIL output and Simulation output is %f', max(diffImg(:)));
After clearing the PIL MEX function, profiling results are available.
Configure the report generator and open the profiling report.
TimerTicksPerSecond holds the target hardware clock frequency.
executionProfile=getCoderExecutionProfile('fog_rectification'); executionProfile.TimerTicksPerSecond = 2035 * 1e6; report(executionProfile, ... 'Units', 'Seconds', ... 'ScaleFactor', '1e-03', ... 'NumericFormat', '%0.3f');
To remove the example files and return to the original folder, call the
cleanup function. cleanup