Generate HDL Code

Step 4 of 6 in Target NI USRP Radios Workflow

HDL IP core generation enables you to generate a shareable and reusable IP core module from a Simulink^® model automatically. HDL Coder™ generates HDL code from the Simulink blocks. By using a reference design, you can create an IP core that integrates into the radio hardware.

After you are satisfied with the simulation behavior of the hardware subsystem, generate the HDL IP core and integrate it with the SDR reference design.

Configure Output Options

The workflow uses the HDL Code tab in the Simulink Toolstrip to access the HDL code generation options and initiate code generation. The Simulink Toolstrip contains contextual tabs that appear only when you need to access them. To access the HDL Code tab, open the HDL Coder app from the Apps tab on the Simulink Toolstrip.

HDL Code tab in the Simulink toolstrip

In the Output options, select IP Core.
Make sure that the user logic subsystem in your model, the design under test (DUT), is pinned in the Generate Code options. To pin this selection, select the DUT in your Simulink model and click the pin icon.

Configure HDL Code Generation Settings

Open the Configuration Parameters window by clicking Settings in the HDL Code tab.

Navigate to the HDL Code Generation pane.

HDL Code Generation pane in the Configuration Parameters window.

Configure the basic options with these settings.

Parameter	Description	Value	Notes
Generate HDL for	Select the subsystem or model for which HDL code is generated.	Path to top level subsystem in root model	The list includes the path to the root model and to subsystems in the model. The default is the top level subsystem in the root model.
Language	Specify the HDL code generation language.	`Verilog` (default)	The generated HDL code complies with the Verilog-2001 (IEEE^® 1364-2001) standard. Verilog is the only supported language for this workflow.
Code Generation Folder	Specify the target folder for the generated HDL code.	`hdl_prj\hdlsrc` (default)	The default target folder is a subfolder of your working folder, named `hdlsrc`.

Navigate to the Target pane.

HDL Code Generation Target pane in the Configuration Parameters window.

Configure the Target settings according to your requirements.

Workflow Settings

Parameter	Description	Value	Notes
Workflow	Specify the target workflow.	`IP Core Generation` (default)	The setting for this parameter determines the available parameters in the Target pane.
Project Folder	Specify the folder for workflow-specific files.	`' '` (default)	The software stores any created files in this folder, such as the generated IP core or synthesis tool project files. It places the generated HDL code in the directory specified by Code Generation Folder.

Tool and Device Settings

Parameter	Description	Value	Notes
Target Platform	Select the target platform for the generated HDL code.	`USRP N310` \| `USRP N320` \| `USRP N321` \| `USRP X310` \| `USRP X410`	For more information, see Supported Radio Devices.
Synthesis Tool	Select the synthesis tool for targeting the generated HDL code.	`Xilinx Vivado`	For more information about the installation requirements, see Vivado.

Reference Design Settings

Parameter		Description	Value	Notes
Reference Design		Specify the reference Vivado^® project.	`Receive and Transmit Path` (default)	Use this reference design when your DUT includes both input and output data streaming interfaces to and from the radio.
			`Receive Path`	Use this reference design when your DUT includes only input data streaming interfaces from the radio.
			`Transmit Path`	Use this reference design when your DUT includes only output data streaming interfaces to the radio.
Reference Design Tool Version		Select the Synthesis Tool version.	`2019.1` (default)	`Family`, `Device`, `Package`, and `Speed` are populated with default values for this tool version.
Reference Design Parameters	External Memory	Specify whether to buffer data connections to and from the host.	`PL DDR Buffer` (default)	Enable the use of the onboard radio memory buffer for data connections to and from the host, which ensures contiguous data transfer.
	External Memory		`None`	Remove the option to use the onboard radio memory buffer.
	Number of Input Streams	Specify the number of data streaming input ports on the DUT.	Positive integer	N/A
	Number of Output Streams	Specify the number of data streaming output ports on the DUT.	Positive integer	N/A
	Number of Antennas	Specify the number of antenna connections required on the radio.	Positive integer	This number includes antenna connections between the DUT and the radio as well as connections between the host and radio for transmitting and capturing test data using the `capture` and `transmit` functions.
	Sample Rate	Specify the baseband sample rate in S/s.	Positive numeric scalar	The value can be any valid sample rate for the radio device. You can update this later using the `SampleRate` property on the `usrp` System object™.
	BlockID	Specify the ID to give the IP Core block generated from the DUT.	`12345678` (default) \| any 32-bit hexadecimal number	To differentiate between bitstreams, change this value when you create successive IP cores.
	DUT Clock Source	Specify the clock source for the DUT.	`Radio` (default)	The DUT is clocked at the master clock rate (MCR) used by the radio.
	DUT Clock Source	Specify the clock source for the DUT.	`Custom`	You can specify a user-defined DUT clock frequency with the Target Frequency configuration parameter.
	Stream Port FIFO Length	Specify the buffer length in samples for each DUT input and output data streaming port.	`Auto` (default)	The software calculates the buffer length based on the target frequency and the maximum valid MCR of the radio.
	Stream Port FIFO Length		Integer in the range `8` to `2048`	The buffer length is set to the specified value.
	Register Port FIFO Length	Specify the buffer length in samples for each DUT register port.	`Auto` (default)	The software calculates the buffer length based on the target frequency and the maximum valid MCR of the radio.
	Register Port FIFO Length		Integer in the range `8` to `2048`	The buffer length is set to the specified value.

Objective Settings

Parameter	Description	Value	Notes
Target Frequency	Specify the DUT clock frequency.	Maximum MCR of the target radio device (default)	If DUT Clock Source is set to `Radio`, you cannot change this value from the default value. For details, see Supported Master Clock Rates.
Target Frequency	Specify the DUT clock frequency.	Positive numeric scalar	If DUT Clock Source is set to `Custom`, set this value to any frequency in MHz within the supported target frequency range for the radio device.

Map Target Interfaces

In the HDL Code tab, click Target Interface to open the Interface Mapping table in the IP Core editor. To populate the table with your user logic, click the icon.

The Source column contains the DUT input and output ports. For each data streaming interface in your model, the Source column in the interface mapping table contains a data, valid, last, and ready signal. Use the following guidelines for mapping register interfaces and data streaming interfaces to populate the Interface column.

Interface Mapping table in the IP Core editor populated with the DUT ports.

When you have populated the table, click the icon to validate the interface mapping.

Map Register Interfaces

Assign any register input as a Write Register and any register output as a Read Register.

Map Data Streaming Inputs

For the first data streaming input, populate the Interface column with these values.

Data — Assign as Data_In0.
Valid — Assign as Valid_In0.
Last — Assign as Last_In0.
Ready — Assign as Ready_Out0.
End of burst — Assign as EOB_In0 (optional).
Has time — Assign as HasTime_In0 (optional).
Timestamp — Assign as Timestamp_In0 (optional).

For each consecutive data streaming input, assign these values and increment the appended number, for example, assign Data_In1 for the data port of the second streaming input.

For each data streaming input, open the Set Interface Options window by clicking Options. Assign a source connection from the following options.

Radio — The streaming input port receives samples from the radio front end.
Host — The streaming input port receives samples from the host.
PL DDR Buffer — The streaming input port receives samples from the host through the PL DDR buffer, which ensures contiguous samples.

Assign the stream buffer size as a number of samples, where each sample is 4 bytes. The default is the maximum possible buffer size. For optimal usage of FPGA memory resources, set the buffer size to a power of two.

Map Data Streaming Outputs

For the first data streaming output, populate the Interface column with the following values.

Data — Assign as Data_Out0.
Valid — Assign as Valid_Out0.
Last — Assign as Last_Out0.
Ready — Assign as Ready_In0.
End of burst — Assign as EOB_Out0 (optional).
Has time — Assign as HasTime_Out0 (optional).
Timestamp — Assign as Timestamp_Out0 (optional).

For each consecutive data streaming output, assign these values and increment the appended number. For example, assign Data_Out1 for the data port of the second streaming input.

For each data streaming output, open the Set Interface Options window by clicking Options. Assign a sink connection from the following options.

Radio — The streaming output port sends samples to the radio front end.
Host — The streaming output port sends samples to the host.
PL DDR Buffer — The streaming output port sends samples to the host through the PL DDR buffer, which ensures contiguous samples.

Generate IP Core

Note

This step is handled automatically in Generate Bitstream and Program FPGA. Use this step to generate the IP core files without building a bitstream.

To generate an IP core for your user logic without building a bitstream, in the HDL Code tab, click Generate IP Core. This generates an RFNoC compatible IP core that you can integrate into a design outside of MATLAB^® and Simulink. The IP core files are generated in a folder named rfnoc within the project folder that you set up in the Configure HDL Code Generation Settings step.